Bart J. Thijssen

20182019
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  • 5 Similar Profiles
FIR filters Engineering & Materials Science
Transconductance Engineering & Materials Science
Digital to analog conversion Engineering & Materials Science
Phase noise Engineering & Materials Science
Bandwidth Engineering & Materials Science
Clocks Engineering & Materials Science
Detectors Engineering & Materials Science
Phase locked loops Engineering & Materials Science

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Research Output 2018 2019

  • 2 Article
  • 1 Conference contribution
  • 1 Patent
24 Downloads (Pure)

A 0.06–3.4-MHz 92-μW Analog FIR Channel Selection Filter With Very Sharp Transition Band for IoT Receivers

Thijssen, B. J., Klumperink, E. A. M., Quinlan, P. & Nauta, B., 25 Sep 2019, IEEE 45th European Solid State Circuits Conference, ESSCIRC 2019. Piscataway, NJ: IEEE Solid-State Circuits Society, 4 p. (IEEE European Solid State Circuits Conference (ESSCIRC); vol. 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Open Access
File
FIR filters
Transconductance
Digital to analog conversion
Bandwidth
Internet of things
63 Downloads (Pure)

A 0.06–3.4-MHz 92- μ W Analog FIR Channel Selection Filter With Very Sharp Transition Band for IoT Receivers

Thijssen, B. J., Klumperink, E. A. M., Quinlan, P. & Nauta, B., 21 Oct 2019, In : IEEE Solid State Circuits Letters. 2, 9, p. 171-174 4 p.

Research output: Contribution to journalArticleAcademicpeer-review

Open Access
File
FIR filters
Transconductance
Digital to analog conversion
Bandwidth
Internet of things
678 Downloads (Pure)

Feedforward phase noise cancellation exploiting a sub-sampling phase detector

Thijssen, B. J., Klumperink, E. A. M., Quinlan, P. & Nauta, B., 1 Nov 2018, In : IEEE transactions on circuits and systems II: express briefs. 65, 11, p. 1574-1578 5 p.

Research output: Contribution to journalArticleAcademicpeer-review

Open Access
File
Phase noise
Phase locked loops
Sampling
Detectors
Noise abatement

Feedforward phase noise compensation

Thijssen, B. J., Klumperink, E. A. M., Nauta, B. & Quinlan, P., 7 Sep 2018, Patent No. WO2018160569 (A1), Priority date 27 Feb 2018, Priority No. US201762465717P 20170301

Research output: Patent

Open Access
File
Phase noise
Clocks
Delay circuits
Detectors
Compensation and Redress