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Fingerprint Dive into the research topics where Daniel M. Ziener is active. These topic labels come from the works of this person. Together they form a unique fingerprint.

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Field programmable gate arrays (FPGA) Engineering & Materials Science
Watermarking Engineering & Materials Science
Query processing Engineering & Materials Science
Hardware Engineering & Materials Science
Embedded systems Engineering & Materials Science
Throughput Engineering & Materials Science
Processing Engineering & Materials Science
Random access storage Engineering & Materials Science

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Research Output 2005 2019

Pipelined database processing circuit and method

Blott, M., Liu, L., Ziener, D. & Karras, K., 19 Nov 2019, Patent No. 10482129, 11 Apr 2017

Research output: Patent

Open Access
Networks (circuits)
Data storage equipment

Security in Embedded Hardware

Ziener, D., 2019, Universiteit Twente. 130 p.

Research output: Book/ReportBookAcademic

Open Access
2 Citations (Scopus)
5 Downloads (Pure)

A Flexible FPGA-based Inference Architecture for Pruned Deep Neural Networks

Posewsky, T. & Ziener, D., 1 May 2018, Architecture of Computing Systems – ARCS 2018: 31st International Conference, Braunschweig, Germany, April 9–12, 2018, Proceedings. Berekovic, M., Buchty, R., Hamann, H., Koch, D. & Pionteck, T. (eds.). Braunschweig, Germany: Springer, p. 311-323 13 p. (Lecture notes in computer science; vol. 10793).

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Field programmable gate arrays (FPGA)
Neural networks
Chemical activation
Deep neural networks

Configuration Tampering of BRAM-based AES Implementations on FPGAs

Ziener, D., Pirkl, J. & Teich, J., 3 Dec 2018, (Accepted/In press) 2018 International Conference on ReConFigurable Computing and FPGAs. IEEE Computer Society, 7 p.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Random access storage
Field programmable gate arrays (FPGA)
Reverse engineering
Data storage equipment
4 Citations (Scopus)
1 Downloads (Pure)

Throughput optimizations for FPGA-based deep neural network inference

Posewsky, T. & Ziener, D., 1 Jul 2018, In : Microprocessors and microsystems. 60, p. 151-161 11 p.

Research output: Contribution to journalArticleAcademicpeer-review

Field programmable gate arrays (FPGA)
Data transfer
Embedded systems
Pattern recognition

Press / Media