Daniel M. Ziener

dr.ing., habil.

Computer Architecture Design and Test for Embedded Systems

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2 Similar Profiles

Field programmable gate arrays (FPGA) Engineering & Materials Science

Watermarking Engineering & Materials Science

Query processing Engineering & Materials Science

Hardware Engineering & Materials Science

Embedded systems Engineering & Materials Science

Throughput Engineering & Materials Science

Random access storage Engineering & Materials Science

Adders Engineering & Materials Science

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Research Output 2005 2019

36 Conference contribution
7 Article
2 Book editing
2 Book
7 More

Security in Embedded Hardware

Ziener, D., 2019, Universiteit Twente. 130 p.

Research output: Book/Report › Book › Academic

Open Access

File

1 Citation (Scopus)

5 Downloads (Pure)

A Flexible FPGA-based Inference Architecture for Pruned Deep Neural Networks

Posewsky, T. & Ziener, D., 1 May 2018, Architecture of Computing Systems – ARCS 2018: 31st International Conference, Braunschweig, Germany, April 9–12, 2018, Proceedings. Berekovic, M., Buchty, R., Hamann, H., Koch, D. & Pionteck, T. (eds.). Braunschweig, Germany: Springer, p. 311-323 13 p. (Lecture notes in computer science; vol. 10793).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Field programmable gate arrays (FPGA)

Neural networks

Neurons

Chemical activation

Deep neural networks

Configuration Tampering of BRAM-based AES Implementations on FPGAs

Ziener, D., Pirkl, J. & Teich, J., 3 Dec 2018, (Accepted/In press) 2018 International Conference on ReConFigurable Computing and FPGAs. IEEE Computer Society, 7 p.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Random access storage

Cryptography

Field programmable gate arrays (FPGA)

Reverse engineering

Data storage equipment

2 Citations (Scopus)

1 Downloads (Pure)

Throughput optimizations for FPGA-based deep neural network inference

Posewsky, T. & Ziener, D., 1 Jul 2018, In : Microprocessors and microsystems. 60, p. 151-161 11 p.

Research output: Contribution to journal › Article › Academic › peer-review

Field programmable gate arrays (FPGA)

Throughput

Data transfer

Embedded systems

Pattern recognition

4 Citations (Scopus)

1 Downloads (Pure)

FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs

Echavarria, J., Wildermann, S., Becher, A., Teich, J. & Ziener, D., 15 May 2017, 2016 International Conference on Field-Programmable Technology, FPT 2016. IEEE, p. 213-216 4 p. 7929536

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Adders

Field programmable gate arrays (FPGA)

calculus

Embedded systems

logic