20052019

Research output per year

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Research Output

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2019

Optimizing FPGA-Based Streaming Applications for Throughput Using Pipelining

Asghar, S. M. A., Van Loo, R., Kruiper, T. & Ziener, D., Dec 2019, Proceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019. Los Alamitos, California: IEEE, p. 351-354 4 p. 8977878. (Proceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019; vol. 2019-December).

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Open Access
File
2 Downloads (Pure)
2018

A Flexible FPGA-based Inference Architecture for Pruned Deep Neural Networks

Posewsky, T. & Ziener, D., 1 May 2018, Architecture of Computing Systems – ARCS 2018: 31st International Conference, Braunschweig, Germany, April 9–12, 2018, Proceedings. Berekovic, M., Buchty, R., Hamann, H., Koch, D. & Pionteck, T. (eds.). Braunschweig, Germany: Springer, p. 311-323 13 p. (Lecture notes in computer science; vol. 10793).

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

2 Citations (Scopus)
5 Downloads (Pure)

Configuration Tampering of BRAM-based AES Implementations on FPGAs

Ziener, D., Pirkl, J. & Teich, J., 2018, 2018 International Conference on ReConFigurable Computing and FPGAs. IEEE Computer Society, 7 p.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

2 Downloads (Pure)
2017

FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs

Echavarria, J., Wildermann, S., Becher, A., Teich, J. & Ziener, D., 15 May 2017, 2016 International Conference on Field-Programmable Technology, FPT 2016. IEEE, p. 213-216 4 p. 7929536

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

7 Citations (Scopus)
1 Downloads (Pure)
2016

A co-design approach for accelerated SQL query processing via FPGA-based data filtering

Becher, A., Ziener, D., Meyer-Wegener, K. & Teich, J., 25 Jan 2016, 2015 International Conference on Field Programmable Technology, FPT 2015. IEEE, p. 192-195 4 p. 7393148

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

14 Citations (Scopus)

A LUT-Based Approximate Adder

Becher, A., Echavarria, J., Ziener, D., Wildermann, S. & Teich, J., 16 Aug 2016, 24th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM). Piscataway, NJ: IEEE, p. 27 1 p. 7544739

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

9 Citations (Scopus)
1 Downloads (Pure)

Efficient deep neural network acceleration through FPGA-based batch processing

Posewsky, T. & Ziener, D., 2016, 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016. IEEE, 7857167

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

3 Citations (Scopus)
2015

Approximate Adder Structures on FPGAs

Becher, A., Echavarria, J., Ziener, D. & Teich, J., 1 Oct 2015, Proceedings of the Workshop on Approximate Computing.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

File
258 Downloads (Pure)

Reliability of space-grade vs. COTS SRAM-based FPGA in N-modular redundancy

Glein, R., Rittner, F., Becher, A., Ziener, D., Frickel, J., Teich, J. & Heuberger, A., 31 Aug 2015, 2015 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2015. Piscataway, NJ: IEEE, 7231159

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

15 Citations (Scopus)
2014

An Automatic Netlist and Floorplanning Approach to Improve the MTTR of Scrubbing Techniques (Abstract Only)

Schmidt, B., Ziener, D. & Teich, J., 2014, Proceedings of the 2014 ACM/SIGDA International Symposium on Field-programmable Gate Arrays. ACM/Sheridan, p. 257-257 1 p.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

A Netlist Analysis Approach to Classify FPGA Configuration Bits in order to Optimize Scrubbing

Schmidt, B., Ziener, D. & Teich, J., 2014, Proceedings of the 8th HiPEAC Workshop on Reconfigurable Computing (WRC). 1 p.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

A self-adaptive SEU mitigation system for FPGAs with an internal block RAM radiation particle sensor

Glein, R., Schmidt, B., Rittner, F., Teich, J. & Ziener, D., 21 Jul 2014, 2014 IEEE 22nd International Symposium on Field-Programmable Custom Computing Machines (FCCM). Piscataway, NJ: IEEE, p. 251-258 8 p. 6861641

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

25 Citations (Scopus)

Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration

Becher, A., Bauer, F., Ziener, D. & Teich, J., 16 Oct 2014, Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014. IEEE, 6927502

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

21 Citations (Scopus)
1 Downloads (Pure)

Minimizing scrubbing effort through automatic netlist partitioning and floorplanning

Schmidt, B., Ziener, D. & Teich, J., 27 Nov 2014, Proceedings - IEEE 28th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2014. IEEE Computer Society, p. 299-304 6 p. 6969403

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

3 Citations (Scopus)
1 Downloads (Pure)
2013

Acceleration of SQL restrictions and aggregations through fpga-based dynamic partial reconfiguration

Dennl, C., Ziener, D. & Teich, J., 2013, 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines. p. 25-28 4 p. 6545990

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Open Access
File
31 Citations (Scopus)
171 Downloads (Pure)
2012

FPGA-based testbed for timing behavior evaluation of the Controller Area Network (CAN)

Ziermann, T., Butiu, A., Teich, J. & Ziener, D., 2012, 2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2012. 6416750

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

On-the-fly composition of FPGA-based SQL query accelerators using a partially reconfigurable module library

Dennl, C., Ziener, D. & Teich, J., 2012, 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines 2012. p. 45-52 8 p. 6239790

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

49 Citations (Scopus)

Partial reconfiguration on FPGAs in practice - Tools and applications

Koch, D., Torresen, J., Beckhoff, C., Ziener, D., Dennl, C., Breuer, V., Teich, J., Feilen, M. & Stechele, W., 2012, ARCS 2012. 6222217

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

13 Citations (Scopus)
2 Downloads (Pure)

System Level Synthesis Flow for Self-adaptive Multi-mode Reconfigurable Systems

Wildermann, S., Reimann, F., Ziener, D. & Teich, J., 1 Sep 2012, Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS 2012).

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Open Access
File
2 Downloads (Pure)
2011

A Flexible Smart Camera System based on a Partially Reconfigurable Dynamic FPGA-SoC

Ziener, D., Wildermann, S., Oetken, A., Weichslgartner, A. & Teich, J., 1 Sep 2011, Proceedings of the Workshop on Computer Vision on Low-Power Reconfigurable Architectures at the FPL 2011. p. 29-30 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Open Access
File
3 Downloads (Pure)

An FPGA implementation of a threat-based strategy for Connect6

Ziermann, T., Schmidt, B., Mühlenthaler, M., Ziener, D., Angermeier, J. & Teich, J., 2011, 2011 International Conference on Field-Programmable Technology (FPT). Oiscataway, NJ: IEEE, 6133250

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Runtime stress-aware replica placement on reconfigurable devices under safety constraints

Angermeier, J., Ziener, D., Glaß, M. & Teich, J., 2011, 2011 International Conference on Field-Programmable Technology (FPT). Piscataway, NJ: IEEE, 6133247

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

3 Citations (Scopus)

Stress-aware module placement on reconfigurable devices

Angermeier, J., Ziener, D., Glaß, M. & Teich, J., 2011, 21st International Conference on Field Programmable Logic and Applications, FPL 2011. p. 277-281 5 p. 6044829

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

14 Citations (Scopus)

Symbolic design space exploration for multi-mode reconfigurable systems

Wildermann, S., Reimann, F., Ziener, D. & Teich, J., 2011, 7th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS'11. p. 129-138 10 p.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

16 Citations (Scopus)

Unifying partitioning and placement for SAT-based exploration of heterogeneous reconfigurable SOCS

Wildermann, S., Teich, J. & Ziener, D., 2011, 2011 21st International Conference on Field Programmable Logic and Applications. p. 429-434 6 p. 6044858

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

4 Citations (Scopus)

Verifying the Authorship of Embedded IP Cores: Watermarking and Core Identification Techniques

Teich, J. & Ziener, D., 1 Jul 2011, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'11).

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Open Access
File
2 Downloads (Pure)
2010

A rapid prototyping system for error-resilient multi-processor systems-on-chip

May, M., Wehn, N., Bouajila, A., Zeppenfeld, J., Stechele, W., Herkersdorf, A., Ziener, D. & Teich, J., 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010). p. 375-380 6 p. 5457176

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

10 Citations (Scopus)

Multiplexing methods for power watermarking

Ziener, D., Baueregger, F. & Teich, J., 2010, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010. p. 36-41 6 p. 5513118

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

11 Citations (Scopus)

New Directions for FPGA IP Core Watermarking and Identification

Ziener, D. & Teich, J., 1 Dec 2010, Dagstuhl Seminar 10281 Proceedings.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademic

Open Access
File
8 Downloads (Pure)

Using the power side channel of FPGAs for communication

Ziener, D., Baueregger, F. & Teich, J., 2010, 18th IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2010. p. 237-244 8 p. 5474043

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

16 Citations (Scopus)
2008

Concepts for autonomous control flow checking for embedded CPUs

Ziener, D. & Teich, J., 2008, Autonomic and Trusted Computing: 5th International Conference, ATC 2008, Proceedings. Rong, C., Jaatun, M. G., Sandnes, F. E., Yang, L. T. & Ma, J. (eds.). p. 234-248 15 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 5060 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

3 Citations (Scopus)
1 Downloads (Pure)

Netlist-level IP protection by watermarking for LUT-Based FPGAs

Schmid, M., Ziener, D. & Teich, J., 2008, 2008 International Conference on Field-Programmable Technology, ICFPT 2008. p. 209-216 8 p. 4762385

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

36 Citations (Scopus)
2007

Autonomic MPSoCs for Reliable Systems

Stechele, W., Bringmann, O., Ernst, R., Herkersdorf, A., Hojenski, K., Janacik, P., Rammig, F., Teich, J., Wehn, N., Zeppenfeld, J. & Ziener, D., 1 Mar 2007, Proceedings of Zuverlässigkeit und Entwurf (ZuD 2007). Munich, Germany, p. 137-138 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Concepts for Autonomic Integrated Systems

Stechele, W., Bringmann, O., Ernst, R., Herkersdorf, A., Hojenski, K., Janacik, P., Rammig, F., Teich, J., Wehn, N., Zeppenfeld, J. & Ziener, D., 1 Jun 2007, Proceedings of edaWorkshop07. Munich, Germany

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

2006

A Method for Measuring Time Delay Behavior of Antennas

Adel, H., Hofmann, G., Wansch, R. & Ziener, D., 1 May 2006, Proceedings of First AMTA Europe Symposium. Munich, Germany

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

FPGA core watermarking based on power signature analysis

Ziener, D. & Teich, J., 2006, 2006 IEEE International Conference on Field Programmable Technology, FPT 2006. p. 205-212 8 p. 4042435

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

13 Citations (Scopus)

Identifying FPGA IP-cores based on lookup table content analysis

Ziener, D., Aßmus, S. & Teich, J., 2006, 2006 International Conference on Field Programmable Logic and Applications, FPL. p. 481-486 6 p. 4101017

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

23 Citations (Scopus)