20052019

Research output per year

If you made any changes in Pure these will be visible here soon.

Research Output

Filter
Article
2018

Throughput optimizations for FPGA-based deep neural network inference

Posewsky, T. & Ziener, D., 1 Jul 2018, In : Microprocessors and microsystems. 60, p. 151-161 11 p.

Research output: Contribution to journalArticleAcademicpeer-review

Open Access
File
4 Citations (Scopus)
18 Downloads (Pure)
2017

Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning

Schmidt, B., Ziener, D., Teich, J. & Zöllner, C., 1 Sep 2017, In : Integration, the VLSI Journal. 59, p. 98-108 11 p.

Research output: Contribution to journalArticleAcademicpeer-review

1 Citation (Scopus)
2 Downloads (Pure)
2016

FPGA-based dynamically reconfigurable SQL query processing

Ziener, D., Bauer, F., Becher, A., Dennl, C., Meyer-Wegener, K., Schurfeld, U., Teich, J., Vogt, J. S. & Weber, H., 1 Aug 2016, In : ACM Transactions on Reconfigurable Technology and Systems. 9, 4, 25.

Research output: Contribution to journalArticleAcademicpeer-review

13 Citations (Scopus)
2013

Symbolic system-level design methodology for multi-mode reconfigurable systems

Wildermann, S., Reimann, F., Ziener, D. & Teich, J., 1 Jun 2013, In : Design Automation for Embedded Systems. 17, 2, p. 343-375 33 p.

Research output: Contribution to journalArticleAcademicpeer-review

4 Citations (Scopus)
2009

AIS - Autonomous Integrated Systems

Schöber, V., Bringmann, O., Herkersdorf, A., Stechele, W., Wehn, N., May, M., Ziener, D., Bouajila, A., Baldin, D., Zeppenfeld, J., Sanders, B., Teich, J., Sebastian, M., Ernst, R. & Treytnar, D., 2009, In : Newsletter Edacentrum. 04, p. 05-13 9 p.

Research output: Contribution to journalArticleAcademic

Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs

Ziener, D. & Teich, J., Jun 2009, In : International journal of autonomous and adaptive communications systems. 2, 3, p. 256-275 20 p.

Research output: Contribution to journalArticleAcademicpeer-review

5 Citations (Scopus)
2008

Power signature watermarking of IP cores for FPGAs

Ziener, D. & Teich, J., Apr 2008, In : Journal of signal processing systems for signal image and video technology. 51, 1, p. 123-136 14 p.

Research output: Contribution to journalArticleAcademicpeer-review

53 Citations (Scopus)