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Harijot Singh Bindra

20172019
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Fingerprint Dive into the research topics where Harijot Singh Bindra is active. These topic labels come from the works of this person. Together they form a unique fingerprint.

  • 5 Similar Profiles
Sampling Engineering & Materials Science
Electric potential Engineering & Materials Science
Energy utilization Engineering & Materials Science
Digital to analog conversion Engineering & Materials Science
Rails Engineering & Materials Science
Electric power utilization Engineering & Materials Science
Electric delay lines Engineering & Materials Science
Capacitors Engineering & Materials Science

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Research Output 2017 2019

  • 5 Conference contribution
  • 1 Article
  • 1 PhD Thesis - Research UT, graduation UT
22 Downloads (Pure)

A 0.2 - 8 MS/s 10b flexible SAR ADC Achieving 0.35 - 2.5 fJ/Conv-Step and using self-quenched dynamic bias comparator

Bindra, H. S., Annema, A-J., Louwsma, S. M. & Nauta, B., 29 Jul 2019, 2019 Symposium on VLSI Circuits: Digest of Technical Papers. Kyoto, Japan: IEEE, p. 74 75 p.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Open Access
File
Electric delay lines
Sampling
Electric potential
1 Citation (Scopus)
24 Downloads (Pure)

A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply

Bindra, H. S., Annema, A. J., Wienk, G. J. M., Nauta, B. & Louwsma, S., 17 Apr 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC) . Austin, TX, USA: IEEE, 8780150. (Proceedings of the Custom Integrated Circuits Conference; vol. 2019-April).

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Open Access
File
Rails
Electric potential
25 Downloads (Pure)

Low Energy Design Techniques For Data Converters

Bindra, H. S., 13 Nov 2019, Enschede: University of Twente. 163 p.

Research output: ThesisPhD Thesis - Research UT, graduation UTAcademic

Open Access
File
Digital to analog conversion
Energy utilization
Electric potential
Capacitors
Internet
8 Citations (Scopus)
327 Downloads (Pure)

A 1.2-V Dynamic bias latch-type comparator in 65-nm CMOS with 0.4-mV input noise

Bindra, H. S., Lokin, C. E., Schinkel, D., Annema, A. J. & Nauta, B., 1 Jul 2018, In : IEEE journal of solid-state circuits. 53, 7, p. 1902-1912 11 p.

Research output: Contribution to journalArticleAcademicpeer-review

Open Access
File
Energy utilization
Electric potential
Capacitors
6 Citations (Scopus)
615 Downloads (Pure)

A 30fJ/comparison dynamic bias comparator

Bindra, H. S., Lokin, C. E., Annema, A. J. & Nauta, B., 12 Sep 2017, ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference . Leuven, Belgium: IEEE Solid-State Circuits Society, p. 71-74 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Open Access
File
Light amplifiers
Flip flop circuits
Energy utilization
Electric potential