1.2 Racing Down the Slopes of Moore's Law

Bram Nauta*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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Since its inception, Moore's Law has been the driving force for IC design. Although during the first decade, 'everything' seemed to be better, however, we lost the scaling of processor clock speed and RF transistor speed, and now it looks as if power efficiency of digital gates will stall. What remains is scaling in transistor count and cost-per-function, thanks to 3D integration.Thus, this is an excellent moment to reconsider how we design for analog and digital signal processing. The higher the required signal-to-noise ratio (SNR), the more power-efficient digital signal processing is compared to analog. Pure analog processing remains more efficient only for ~ 30 dB SNR or less. In the case of digital processing, the conversion from analog to digital should therefore be made as early in the signal chain as possible. Thanks to the figure-of-merit race, analog-to-digital converters (ADCs) have experienced a tremendous win in power efficiency. However, these ADCs require a large input voltage swing while the input signals to be converted, from an antenna or sensor interface, are usually much smaller. Therefore, RF and analog front-ends are needed, which consume much more power than the ADCs to be driven.Let us re-think these analog front-ends. Can we still efficiently design these front-ends in future CMOS? Do we need so much linear amplification? Do we need active linear circuits at all? Can we not use 'digital' components to replace the analog front-ends and ADCs? This paper aims to look at digital and analog processing trends from technology and design fundamentals points of view. We will first zoom out on asymptotic trends in technology scaling and try to identify future design opportunities and challenges. For circuit design, fundamental limits linking power, speed, and accuracy will be reviewed to gain insight into the implications of how we design circuits the way we currently do. This paper aims to create awareness and gives a new vision of designing analog circuits.

Original languageEnglish
Title of host publication2024 IEEE International Solid-State Circuits Conference (ISSCC)
Number of pages8
ISBN (Electronic)979-8-3503-0620-0
Publication statusPublished - 19 Feb 2024
EventIEEE International Solid-State Circuits Conference, ISSCC 2024 - San Francisco, United States
Duration: 18 Feb 202422 Feb 2024


ConferenceIEEE International Solid-State Circuits Conference, ISSCC 2024
Abbreviated titleISSCC 2024
Country/TerritoryUnited States
CitySan Francisco


  • Band-pass filter
  • Radio frequency
  • Sigma-delta modulation
  • Time-frequency analysis
  • Capacitors
  • voltage
  • Transistors


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