1.9 nm wide ultra-high aspect-ratio bulk-si FinFETs

Vladimir Jovanović*, Mirko Poljak, Tomislav Suligoj, Yann Civale, Lis K. Nanver

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

2 Citations (Scopus)

Abstract

FinFETs are foreseen as a solution for the suppression of short-channel effects (SCE) from the 22 nm node onwards because of their superior electrostatic integrity achieved with a fabrication technique that is similar to bulk CMOS processes [1]. To keep SCEs under control the width of the etched fins must be reduced as the gatelength is scaled down. The fin-height is typically reduced as well to keep the same aspect ratio between the finheight and fin-width which allows the same fin-etching processes to be used also for smaller devices. This work focuses on FinFETs with high aspect-ratio and thus a wide MOSFET channels in each fin, which translates into higher device density per chip area and more efficient use of the silicon real-estate. Moreover, in analog applications where multi-fin devices are required for wider transistors, a small number of taller fins is preferable to a large number of shorter fins in terms of gate resistance and gate capacitance which improves high-frequency performance [2, 3]. The fabrication process is designed to keep the fin-width in the 10 nm range while at the same time tall fins are etched [4].

Original languageEnglish
Title of host publication67th Device Research Conference, DRC 2009
Pages261-262
Number of pages2
DOIs
Publication statusPublished - 11 Dec 2009
Externally publishedYes
Event67th Device Research Conference, DRC 2009 - University Park, United States
Duration: 22 Jun 200924 Jun 2009

Publication series

NameDevice Research Conference - Conference Digest, DRC
ISSN (Print)1548-3770

Conference

Conference67th Device Research Conference, DRC 2009
Abbreviated titleDRC 2009
CountryUnited States
CityUniversity Park
Period22/06/0924/06/09

Fingerprint

Aspect ratio
Fabrication
Electrostatics
Etching
Transistors
Capacitance
Silicon
FinFET

Cite this

Jovanović, V., Poljak, M., Suligoj, T., Civale, Y., & Nanver, L. K. (2009). 1.9 nm wide ultra-high aspect-ratio bulk-si FinFETs. In 67th Device Research Conference, DRC 2009 (pp. 261-262). [5354923] (Device Research Conference - Conference Digest, DRC). https://doi.org/10.1109/DRC.2009.5354923
Jovanović, Vladimir ; Poljak, Mirko ; Suligoj, Tomislav ; Civale, Yann ; Nanver, Lis K. / 1.9 nm wide ultra-high aspect-ratio bulk-si FinFETs. 67th Device Research Conference, DRC 2009. 2009. pp. 261-262 (Device Research Conference - Conference Digest, DRC).
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Jovanović, V, Poljak, M, Suligoj, T, Civale, Y & Nanver, LK 2009, 1.9 nm wide ultra-high aspect-ratio bulk-si FinFETs. in 67th Device Research Conference, DRC 2009., 5354923, Device Research Conference - Conference Digest, DRC, pp. 261-262, 67th Device Research Conference, DRC 2009, University Park, United States, 22/06/09. https://doi.org/10.1109/DRC.2009.5354923

1.9 nm wide ultra-high aspect-ratio bulk-si FinFETs. / Jovanović, Vladimir; Poljak, Mirko; Suligoj, Tomislav; Civale, Yann; Nanver, Lis K.

67th Device Research Conference, DRC 2009. 2009. p. 261-262 5354923 (Device Research Conference - Conference Digest, DRC).

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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Jovanović V, Poljak M, Suligoj T, Civale Y, Nanver LK. 1.9 nm wide ultra-high aspect-ratio bulk-si FinFETs. In 67th Device Research Conference, DRC 2009. 2009. p. 261-262. 5354923. (Device Research Conference - Conference Digest, DRC). https://doi.org/10.1109/DRC.2009.5354923