20 Million Patterns Per Second VLSI Neural Network Pattern Classifier

P. Masa, K. Hoen, Hans Wallinga, L. Larsson, H.J. Behrend, W. Zimmermann

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    Abstract

    A special purpose neural IC is described which will be utilised in a data-acquisition system in DESY (Deutsches Elektronen Synchrotron). The analog CMOS VLSI chip implements a 70×4×1 fully interconnected feed-forward network and is capable of classifying 70 dimensional data-vectors within 50 ns. The high speed is essential for the real-time data processing and data-reduction. The classifier has to perform fixed function, therefore programming is not essential. The neural chip is under fabrication with 2.5 μm double metal CMOS process, occupies 65×4 mm2 silicon area, dissipates 2W at 5V power supply, performs 6 billion multiplications per second and has 1.5 GBytes/s equivalent input bandwidth.
    Original languageEnglish
    Title of host publicationICANN '93
    Subtitle of host publicationProceedings of the International Conference on Artificial Neural Networks Amsterdam, The Netherlands 13–16 September 1993
    EditorsStan Gielen, Bert Kappen
    Place of PublicationLondon
    PublisherSpringer
    Pages1058-1061
    ISBN (Electronic)978-1-4471-2063-6
    ISBN (Print)978-3-540-19839-0
    DOIs
    Publication statusPublished - 14 Dec 1993
    EventInternational Conference on Artificial Neural Networks, ICANN 1993 - Amsterdam, Netherlands
    Duration: 13 Sep 199316 Sep 1993

    Conference

    ConferenceInternational Conference on Artificial Neural Networks, ICANN 1993
    Abbreviated titleICANN
    CountryNetherlands
    CityAmsterdam
    Period13/09/9316/09/93

    Fingerprint

    Synchrotrons
    Data acquisition
    Data reduction
    Classifiers
    Neural networks
    Bandwidth
    Fabrication
    Silicon
    Metals

    Keywords

    • Separation boundary
    • Track segment
    • Circuit block
    • Voltage inverter
    • Neural chip

    Cite this

    Masa, P., Hoen, K., Wallinga, H., Larsson, L., Behrend, H. J., & Zimmermann, W. (1993). 20 Million Patterns Per Second VLSI Neural Network Pattern Classifier. In S. Gielen, & B. Kappen (Eds.), ICANN '93: Proceedings of the International Conference on Artificial Neural Networks Amsterdam, The Netherlands 13–16 September 1993 (pp. 1058-1061). London: Springer. https://doi.org/10.1007/978-1-4471-2063-6_313
    Masa, P. ; Hoen, K. ; Wallinga, Hans ; Larsson, L. ; Behrend, H.J. ; Zimmermann, W. / 20 Million Patterns Per Second VLSI Neural Network Pattern Classifier. ICANN '93: Proceedings of the International Conference on Artificial Neural Networks Amsterdam, The Netherlands 13–16 September 1993. editor / Stan Gielen ; Bert Kappen. London : Springer, 1993. pp. 1058-1061
    @inproceedings{e101c589d2bc4381b88ef9ce34332d63,
    title = "20 Million Patterns Per Second VLSI Neural Network Pattern Classifier",
    abstract = "A special purpose neural IC is described which will be utilised in a data-acquisition system in DESY (Deutsches Elektronen Synchrotron). The analog CMOS VLSI chip implements a 70×4×1 fully interconnected feed-forward network and is capable of classifying 70 dimensional data-vectors within 50 ns. The high speed is essential for the real-time data processing and data-reduction. The classifier has to perform fixed function, therefore programming is not essential. The neural chip is under fabrication with 2.5 μm double metal CMOS process, occupies 65×4 mm2 silicon area, dissipates 2W at 5V power supply, performs 6 billion multiplications per second and has 1.5 GBytes/s equivalent input bandwidth.",
    keywords = "Separation boundary, Track segment, Circuit block, Voltage inverter, Neural chip",
    author = "P. Masa and K. Hoen and Hans Wallinga and L. Larsson and H.J. Behrend and W. Zimmermann",
    year = "1993",
    month = "12",
    day = "14",
    doi = "10.1007/978-1-4471-2063-6_313",
    language = "English",
    isbn = "978-3-540-19839-0",
    pages = "1058--1061",
    editor = "Stan Gielen and Bert Kappen",
    booktitle = "ICANN '93",
    publisher = "Springer",

    }

    Masa, P, Hoen, K, Wallinga, H, Larsson, L, Behrend, HJ & Zimmermann, W 1993, 20 Million Patterns Per Second VLSI Neural Network Pattern Classifier. in S Gielen & B Kappen (eds), ICANN '93: Proceedings of the International Conference on Artificial Neural Networks Amsterdam, The Netherlands 13–16 September 1993. Springer, London, pp. 1058-1061, International Conference on Artificial Neural Networks, ICANN 1993, Amsterdam, Netherlands, 13/09/93. https://doi.org/10.1007/978-1-4471-2063-6_313

    20 Million Patterns Per Second VLSI Neural Network Pattern Classifier. / Masa, P.; Hoen, K.; Wallinga, Hans; Larsson, L.; Behrend, H.J.; Zimmermann, W.

    ICANN '93: Proceedings of the International Conference on Artificial Neural Networks Amsterdam, The Netherlands 13–16 September 1993. ed. / Stan Gielen; Bert Kappen. London : Springer, 1993. p. 1058-1061.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    TY - GEN

    T1 - 20 Million Patterns Per Second VLSI Neural Network Pattern Classifier

    AU - Masa, P.

    AU - Hoen, K.

    AU - Wallinga, Hans

    AU - Larsson, L.

    AU - Behrend, H.J.

    AU - Zimmermann, W.

    PY - 1993/12/14

    Y1 - 1993/12/14

    N2 - A special purpose neural IC is described which will be utilised in a data-acquisition system in DESY (Deutsches Elektronen Synchrotron). The analog CMOS VLSI chip implements a 70×4×1 fully interconnected feed-forward network and is capable of classifying 70 dimensional data-vectors within 50 ns. The high speed is essential for the real-time data processing and data-reduction. The classifier has to perform fixed function, therefore programming is not essential. The neural chip is under fabrication with 2.5 μm double metal CMOS process, occupies 65×4 mm2 silicon area, dissipates 2W at 5V power supply, performs 6 billion multiplications per second and has 1.5 GBytes/s equivalent input bandwidth.

    AB - A special purpose neural IC is described which will be utilised in a data-acquisition system in DESY (Deutsches Elektronen Synchrotron). The analog CMOS VLSI chip implements a 70×4×1 fully interconnected feed-forward network and is capable of classifying 70 dimensional data-vectors within 50 ns. The high speed is essential for the real-time data processing and data-reduction. The classifier has to perform fixed function, therefore programming is not essential. The neural chip is under fabrication with 2.5 μm double metal CMOS process, occupies 65×4 mm2 silicon area, dissipates 2W at 5V power supply, performs 6 billion multiplications per second and has 1.5 GBytes/s equivalent input bandwidth.

    KW - Separation boundary

    KW - Track segment

    KW - Circuit block

    KW - Voltage inverter

    KW - Neural chip

    U2 - 10.1007/978-1-4471-2063-6_313

    DO - 10.1007/978-1-4471-2063-6_313

    M3 - Conference contribution

    SN - 978-3-540-19839-0

    SP - 1058

    EP - 1061

    BT - ICANN '93

    A2 - Gielen, Stan

    A2 - Kappen, Bert

    PB - Springer

    CY - London

    ER -

    Masa P, Hoen K, Wallinga H, Larsson L, Behrend HJ, Zimmermann W. 20 Million Patterns Per Second VLSI Neural Network Pattern Classifier. In Gielen S, Kappen B, editors, ICANN '93: Proceedings of the International Conference on Artificial Neural Networks Amsterdam, The Netherlands 13–16 September 1993. London: Springer. 1993. p. 1058-1061 https://doi.org/10.1007/978-1-4471-2063-6_313