20 Million Patterns Per Second VLSI Neural Network Pattern Classifier

P. Masa, K. Hoen, Hans Wallinga, L. Larsson, H.J. Behrend, W. Zimmermann

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review


    A special purpose neural IC is described which will be utilised in a data-acquisition system in DESY (Deutsches Elektronen Synchrotron). The analog CMOS VLSI chip implements a 70×4×1 fully interconnected feed-forward network and is capable of classifying 70 dimensional data-vectors within 50 ns. The high speed is essential for the real-time data processing and data-reduction. The classifier has to perform fixed function, therefore programming is not essential. The neural chip is under fabrication with 2.5 μm double metal CMOS process, occupies 65×4 mm2 silicon area, dissipates 2W at 5V power supply, performs 6 billion multiplications per second and has 1.5 GBytes/s equivalent input bandwidth.
    Original languageEnglish
    Title of host publicationICANN '93
    Subtitle of host publicationProceedings of the International Conference on Artificial Neural Networks Amsterdam, The Netherlands 13–16 September 1993
    EditorsStan Gielen, Bert Kappen
    Place of PublicationLondon
    ISBN (Electronic)978-1-4471-2063-6
    ISBN (Print)978-3-540-19839-0
    Publication statusPublished - 14 Dec 1993
    EventInternational Conference on Artificial Neural Networks, ICANN 1993 - Amsterdam, Netherlands
    Duration: 13 Sept 199316 Sept 1993


    ConferenceInternational Conference on Artificial Neural Networks, ICANN 1993
    Abbreviated titleICANN


    • Separation boundary
    • Track segment
    • Circuit block
    • Voltage inverter
    • Neural chip


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