20 Million Patterns Per Second VLSI Neural Network Pattern Classifier

P. Masa; K. Hoen; Hans Wallinga; L.  Larsson; H.J. Behrend; W. Zimmermann

doi:10.1007/978-1-4471-2063-6_313

20 Million Patterns Per Second VLSI Neural Network Pattern Classifier

P. Masa
, K. Hoen
, Hans Wallinga
, L. Larsson
, H.J. Behrend
, W. Zimmermann

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

A special purpose neural IC is described which will be utilised in a data-acquisition system in DESY (Deutsches Elektronen Synchrotron). The analog CMOS VLSI chip implements a 70×4×1 fully interconnected feed-forward network and is capable of classifying 70 dimensional data-vectors within 50 ns. The high speed is essential for the real-time data processing and data-reduction. The classifier has to perform fixed function, therefore programming is not essential. The neural chip is under fabrication with 2.5 μm double metal CMOS process, occupies 65×4 mm2 silicon area, dissipates 2W at 5V power supply, performs 6 billion multiplications per second and has 1.5 GBytes/s equivalent input bandwidth.

Original language	English
Title of host publication	ICANN '93
Subtitle of host publication	Proceedings of the International Conference on Artificial Neural Networks Amsterdam, The Netherlands 13–16 September 1993
Editors	Stan Gielen, Bert Kappen
Place of Publication	London
Publisher	Springer
Pages	1058-1061
ISBN (Electronic)	978-1-4471-2063-6
ISBN (Print)	978-3-540-19839-0
DOIs	https://doi.org/10.1007/978-1-4471-2063-6_313
Publication status	Published - 14 Dec 1993
Event	International Conference on Artificial Neural Networks, ICANN 1993 - Amsterdam, Netherlands Duration: 13 Sept 1993 → 16 Sept 1993

Conference

Conference	International Conference on Artificial Neural Networks, ICANN 1993
Abbreviated title	ICANN
Country/Territory	Netherlands
City	Amsterdam
Period	13/09/93 → 16/09/93

Keywords

Separation boundary
Track segment
Circuit block
Voltage inverter
Neural chip

Access to Document

10.1007/978-1-4471-2063-6_313

Cite this

Masa, P., Hoen, K., Wallinga, H., Larsson, L., Behrend, H. J., & Zimmermann, W. (1993). 20 Million Patterns Per Second VLSI Neural Network Pattern Classifier. In S. Gielen, & B. Kappen (Eds.), ICANN '93: Proceedings of the International Conference on Artificial Neural Networks Amsterdam, The Netherlands 13–16 September 1993 (pp. 1058-1061). Springer. https://doi.org/10.1007/978-1-4471-2063-6_313

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title = "20 Million Patterns Per Second VLSI Neural Network Pattern Classifier",

abstract = "A special purpose neural IC is described which will be utilised in a data-acquisition system in DESY (Deutsches Elektronen Synchrotron). The analog CMOS VLSI chip implements a 70×4×1 fully interconnected feed-forward network and is capable of classifying 70 dimensional data-vectors within 50 ns. The high speed is essential for the real-time data processing and data-reduction. The classifier has to perform fixed function, therefore programming is not essential. The neural chip is under fabrication with 2.5 μm double metal CMOS process, occupies 65×4 mm2 silicon area, dissipates 2W at 5V power supply, performs 6 billion multiplications per second and has 1.5 GBytes/s equivalent input bandwidth.",

keywords = "Separation boundary, Track segment, Circuit block, Voltage inverter, Neural chip",

author = "P. Masa and K. Hoen and Hans Wallinga and L. Larsson and H.J. Behrend and W. Zimmermann",

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doi = "10.1007/978-1-4471-2063-6\_313",

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note = "International Conference on Artificial Neural Networks, ICANN 1993, ICANN ; Conference date: 13-09-1993 Through 16-09-1993",

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Masa, P, Hoen, K, Wallinga, H, Larsson, L, Behrend, HJ & Zimmermann, W 1993, 20 Million Patterns Per Second VLSI Neural Network Pattern Classifier. in S Gielen & B Kappen (eds), ICANN '93: Proceedings of the International Conference on Artificial Neural Networks Amsterdam, The Netherlands 13–16 September 1993. Springer, London, pp. 1058-1061, International Conference on Artificial Neural Networks, ICANN 1993, Amsterdam, Netherlands, 13/09/93. https://doi.org/10.1007/978-1-4471-2063-6_313

20 Million Patterns Per Second VLSI Neural Network Pattern Classifier. / Masa, P.; Hoen, K.; Wallinga, Hans et al.
ICANN '93: Proceedings of the International Conference on Artificial Neural Networks Amsterdam, The Netherlands 13–16 September 1993. ed. / Stan Gielen; Bert Kappen. London: Springer, 1993. p. 1058-1061.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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N2 - A special purpose neural IC is described which will be utilised in a data-acquisition system in DESY (Deutsches Elektronen Synchrotron). The analog CMOS VLSI chip implements a 70×4×1 fully interconnected feed-forward network and is capable of classifying 70 dimensional data-vectors within 50 ns. The high speed is essential for the real-time data processing and data-reduction. The classifier has to perform fixed function, therefore programming is not essential. The neural chip is under fabrication with 2.5 μm double metal CMOS process, occupies 65×4 mm2 silicon area, dissipates 2W at 5V power supply, performs 6 billion multiplications per second and has 1.5 GBytes/s equivalent input bandwidth.

AB - A special purpose neural IC is described which will be utilised in a data-acquisition system in DESY (Deutsches Elektronen Synchrotron). The analog CMOS VLSI chip implements a 70×4×1 fully interconnected feed-forward network and is capable of classifying 70 dimensional data-vectors within 50 ns. The high speed is essential for the real-time data processing and data-reduction. The classifier has to perform fixed function, therefore programming is not essential. The neural chip is under fabrication with 2.5 μm double metal CMOS process, occupies 65×4 mm2 silicon area, dissipates 2W at 5V power supply, performs 6 billion multiplications per second and has 1.5 GBytes/s equivalent input bandwidth.

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KW - Track segment

KW - Circuit block

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KW - Neural chip

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Masa P, Hoen K, Wallinga H, Larsson L, Behrend HJ, Zimmermann W. 20 Million Patterns Per Second VLSI Neural Network Pattern Classifier. In Gielen S, Kappen B, editors, ICANN '93: Proceedings of the International Conference on Artificial Neural Networks Amsterdam, The Netherlands 13–16 September 1993. London: Springer. 1993. p. 1058-1061 doi: 10.1007/978-1-4471-2063-6_313

20 Million Patterns Per Second VLSI Neural Network Pattern Classifier

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