2T2M memristor based TCAM cell for low power applications

Yuanfan Yang; J. Mathew; M. Ottavi; S. Pontarelli; D.K. Pradhan

doi:10.1109/DTIS.2015.7127379

2T2M memristor based TCAM cell for low power applications

Yuanfan Yang, J. Mathew, M. Ottavi, S. Pontarelli, D.K. Pradhan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

5 Citations (Scopus)

Abstract

This paper presents a 2-transistors-memristors (2T2M) bitcell for content-addressable memory design suitable for low-power applications. It uses memristors to store data and MOS transistors as access devices. The low power proposed design splits the search lines to search logic 1 and logic 0 separately to reduce the search power consumption. Different word sizes of the proposed bitcells with and without low power structure are simulated, including full parasitics using BPTM, 45nm CMOS technology node to evaluate and compare different performance parameters. The proposed low power design reduces the active power dissipation of about 30% compared to the design with conventional search approach.

Original language	English
Title of host publication	Proceedings - 2015 10th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2015
DOIs	https://doi.org/10.1109/DTIS.2015.7127379
Publication status	Published - 2015
Externally published	Yes
Event	10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2015 - Napoli, Italy Duration: 21 Apr 2015 → 23 Apr 2015 Conference number: 10

Conference

Conference	10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2015
Abbreviated title	DTIS 2015
Country/Territory	Italy
City	Napoli
Period	21/04/15 → 23/04/15

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10.1109/DTIS.2015.7127379

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@inproceedings{cb0e597314c9465790ae16b111601b2b,

title = "2T2M memristor based TCAM cell for low power applications",

abstract = "This paper presents a 2-transistors-memristors (2T2M) bitcell for content-addressable memory design suitable for low-power applications. It uses memristors to store data and MOS transistors as access devices. The low power proposed design splits the search lines to search logic 1 and logic 0 separately to reduce the search power consumption. Different word sizes of the proposed bitcells with and without low power structure are simulated, including full parasitics using BPTM, 45nm CMOS technology node to evaluate and compare different performance parameters. The proposed low power design reduces the active power dissipation of about 30% compared to the design with conventional search approach.",

author = "Yuanfan Yang and J. Mathew and M. Ottavi and S. Pontarelli and D.K. Pradhan",

year = "2015",

doi = "10.1109/DTIS.2015.7127379",

language = "English",

booktitle = "Proceedings - 2015 10th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2015",

note = "10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2015, DTIS 2015 ; Conference date: 21-04-2015 Through 23-04-2015",

}

Yang, Y, Mathew, J, Ottavi, M, Pontarelli, S & Pradhan, DK 2015, 2T2M memristor based TCAM cell for low power applications. in Proceedings - 2015 10th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2015. 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2015, Napoli, Italy, 21/04/15. https://doi.org/10.1109/DTIS.2015.7127379

TY - GEN

T1 - 2T2M memristor based TCAM cell for low power applications

AU - Yang, Yuanfan

AU - Mathew, J.

AU - Ottavi, M.

AU - Pontarelli, S.

AU - Pradhan, D.K.

N1 - Conference code: 10

PY - 2015

Y1 - 2015

N2 - This paper presents a 2-transistors-memristors (2T2M) bitcell for content-addressable memory design suitable for low-power applications. It uses memristors to store data and MOS transistors as access devices. The low power proposed design splits the search lines to search logic 1 and logic 0 separately to reduce the search power consumption. Different word sizes of the proposed bitcells with and without low power structure are simulated, including full parasitics using BPTM, 45nm CMOS technology node to evaluate and compare different performance parameters. The proposed low power design reduces the active power dissipation of about 30% compared to the design with conventional search approach.

AB - This paper presents a 2-transistors-memristors (2T2M) bitcell for content-addressable memory design suitable for low-power applications. It uses memristors to store data and MOS transistors as access devices. The low power proposed design splits the search lines to search logic 1 and logic 0 separately to reduce the search power consumption. Different word sizes of the proposed bitcells with and without low power structure are simulated, including full parasitics using BPTM, 45nm CMOS technology node to evaluate and compare different performance parameters. The proposed low power design reduces the active power dissipation of about 30% compared to the design with conventional search approach.

UR - http://www.scopus.com/inward/record.url?eid=2-s2.0-84942543978&partnerID=MN8TOARS

U2 - 10.1109/DTIS.2015.7127379

DO - 10.1109/DTIS.2015.7127379

M3 - Conference contribution

BT - Proceedings - 2015 10th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2015

T2 - 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2015

Y2 - 21 April 2015 through 23 April 2015

ER -

2T2M memristor based TCAM cell for low power applications

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