Beamforming phased-array receivers aim to increase receiver sensitivity and reject interferers in the spatial domain [1,2]. A receiver with programmable phase shift and high linearity is crucial to cope with interference. Switched-capacitor vector modulators can provide adequate phase shift and linearity [3,4], but so far, at the cost of a high power consumption. As power consumption increases linearly with the number of antenna elements, it is one of the bottlenecks hindering commercialization of beamforming. In this paper, we demonstrate several design techniques on architectural and circuit levels, to reduce the power consumption per element, while still achieving competitive Spurious Free Dynamic Range (SFDR).
|Conference||IEEE International Solid-State Circuits Conference, ISSCC 2014|
|Period||9/02/14 → 13/02/14|