3D Full-Wave Simulation of Stub Length Effect of Vias in High Speed PCB Design

Eric Steenbergen*, Niek Moonen, Frank Leferink

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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Abstract

Throughout this paper, signal integrity (SI) problems in high -speed PCB design have been addressed as being a result of via stubs and fabrication tolerances that are present throughout PCB transmission lines. Robust PCB design must be ensured as signal rise and fall times have shortened, which is modeled within the 3D EM simulation environment of CST Studio. It is shown that the insertion loss of the signal is affected by the resonance frequency of the via stub, and impedance mismatches throughout the transmission lines. Shielding techniques have been investigated to combat these effects on SI, and have shown a significant improvement in bandwidth as a result.

Original languageEnglish
Title of host publicationProceedings 2021 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2021
Place of PublicationPiscataway, NJ
PublisherIEEE
ISBN (Electronic)978-1-7281-7621-5
ISBN (Print)978-1-7281-7622-2
DOIs
Publication statusPublished - 16 Nov 2021
Event2021 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2021 - Nusa Dua - Bali, Indonesia, Bali, Indonesia
Duration: 27 Sep 202130 Sep 2021
https://apemc2021.org/

Publication series

NameProceedings Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC)
PublisherIEEE
Volume2021
ISSN (Print)2162-7673
ISSN (Electronic)2640-7469

Conference

Conference2021 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2021
Abbreviated titleAPEMC 2021
Country/TerritoryIndonesia
CityBali
Period27/09/2130/09/21
Internet address

Keywords

  • EMI
  • impedance mismatches
  • via shielding
  • Via stubs
  • 22/1 OA procedure

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