Abstract
Throughout this paper, signal integrity (SI) problems in high -speed PCB design have been addressed as being a result of via stubs and fabrication tolerances that are present throughout PCB transmission lines. Robust PCB design must be ensured as signal rise and fall times have shortened, which is modeled within the 3D EM simulation environment of CST Studio. It is shown that the insertion loss of the signal is affected by the resonance frequency of the via stub, and impedance mismatches throughout the transmission lines. Shielding techniques have been investigated to combat these effects on SI, and have shown a significant improvement in bandwidth as a result.
| Original language | English |
|---|---|
| Title of host publication | Proceedings 2021 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2021 |
| Place of Publication | Piscataway, NJ |
| Publisher | IEEE |
| ISBN (Electronic) | 978-1-7281-7621-5 |
| ISBN (Print) | 978-1-7281-7622-2 |
| DOIs | |
| Publication status | Published - 16 Nov 2021 |
| Event | 2021 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2021 - Merusaka Nusa, Nusa Dua, Bali, Indonesia Duration: 27 Sept 2021 → 30 Sept 2021 https://apemc2021.org/ |
Publication series
| Name | Proceedings Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC) |
|---|---|
| Publisher | IEEE |
| Volume | 2021 |
| ISSN (Print) | 2162-7673 |
| ISSN (Electronic) | 2640-7469 |
Conference
| Conference | 2021 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2021 |
|---|---|
| Abbreviated title | APEMC |
| Country/Territory | Indonesia |
| City | Nusa Dua, Bali |
| Period | 27/09/21 → 30/09/21 |
| Internet address |
Keywords
- EMI
- impedance mismatches
- via shielding
- Via stubs
- 22/1 OA procedure