45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control

V. Gupta; S. Khandelwal; J. Mathew; M. Ottavi

doi:10.1109/DFT.2018.8602981

45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control

V. Gupta, S. Khandelwal, J. Mathew, M. Ottavi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

7 Citations (Scopus)

Abstract

On-chip SRAM array occupies a large area in the microprocessor ICs. This enforces the technology to reach nano-scale domain. In this domain, minimizing the short channel effects, leakage current and improving reliability of memory cell are significant and challenging. FinFET device reduces the short channel effects, leakage current and enhances the performance of the SRAM cell at 45nm technology node and beyond. This paper presents supply voltage management technique for designing a low-power and variability-aware SRAM cell. In this paper, we propose a FinFET based differential 10T SRAM cell using Drowsy Cache architecture for leakage power reduction at 45nm technology node. The proposed differential 10 T SRAM permits bit interleaving with column-wise write access control, having differential read path, thus, improving reliability of the SRAM cell. The proposed circuit also restricts pseudoread problem, by allowing column-wise write in SRAM cell array. The simulation has been carried out on Cadence Virtuoso at 45nm technology node.

Original language	English
Title of host publication	2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2018
DOIs	https://doi.org/10.1109/DFT.2018.8602981
Publication status	Published - 2019
Externally published	Yes
Event	IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2018 - Chicago, United States Duration: 8 Oct 2018 → 10 Oct 2018

Conference

Conference	IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2018
Abbreviated title	DFT 2018
Country/Territory	United States
City	Chicago
Period	8/10/18 → 10/10/18

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10.1109/DFT.2018.8602981

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title = "45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control",

abstract = "On-chip SRAM array occupies a large area in the microprocessor ICs. This enforces the technology to reach nano-scale domain. In this domain, minimizing the short channel effects, leakage current and improving reliability of memory cell are significant and challenging. FinFET device reduces the short channel effects, leakage current and enhances the performance of the SRAM cell at 45nm technology node and beyond. This paper presents supply voltage management technique for designing a low-power and variability-aware SRAM cell. In this paper, we propose a FinFET based differential 10T SRAM cell using Drowsy Cache architecture for leakage power reduction at 45nm technology node. The proposed differential 10 T SRAM permits bit interleaving with column-wise write access control, having differential read path, thus, improving reliability of the SRAM cell. The proposed circuit also restricts pseudoread problem, by allowing column-wise write in SRAM cell array. The simulation has been carried out on Cadence Virtuoso at 45nm technology node.",

author = "V. Gupta and S. Khandelwal and J. Mathew and M. Ottavi",

year = "2019",

doi = "10.1109/DFT.2018.8602981",

language = "English",

booktitle = "2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2018",

note = "IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2018, DFT 2018 ; Conference date: 08-10-2018 Through 10-10-2018",

}

Gupta, V, Khandelwal, S, Mathew, J & Ottavi, M 2019, 45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control. in 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2018. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2018, Chicago, Illinois, United States, 8/10/18. https://doi.org/10.1109/DFT.2018.8602981

45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control. / Gupta, V.; Khandelwal, S.; Mathew, J. et al.

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2018. 2019.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - Khandelwal, S.

AU - Mathew, J.

AU - Ottavi, M.

PY - 2019

Y1 - 2019

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AB - On-chip SRAM array occupies a large area in the microprocessor ICs. This enforces the technology to reach nano-scale domain. In this domain, minimizing the short channel effects, leakage current and improving reliability of memory cell are significant and challenging. FinFET device reduces the short channel effects, leakage current and enhances the performance of the SRAM cell at 45nm technology node and beyond. This paper presents supply voltage management technique for designing a low-power and variability-aware SRAM cell. In this paper, we propose a FinFET based differential 10T SRAM cell using Drowsy Cache architecture for leakage power reduction at 45nm technology node. The proposed differential 10 T SRAM permits bit interleaving with column-wise write access control, having differential read path, thus, improving reliability of the SRAM cell. The proposed circuit also restricts pseudoread problem, by allowing column-wise write in SRAM cell array. The simulation has been carried out on Cadence Virtuoso at 45nm technology node.

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M3 - Conference contribution

BT - 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2018

T2 - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2018

Y2 - 8 October 2018 through 10 October 2018

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45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control

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