On-chip SRAM array occupies a large area in the microprocessor ICs. This enforces the technology to reach nano-scale domain. In this domain, minimizing the short channel effects, leakage current and improving reliability of memory cell are significant and challenging. FinFET device reduces the short channel effects, leakage current and enhances the performance of the SRAM cell at 45nm technology node and beyond. This paper presents supply voltage management technique for designing a low-power and variability-aware SRAM cell. In this paper, we propose a FinFET based differential 10T SRAM cell using Drowsy Cache architecture for leakage power reduction at 45nm technology node. The proposed differential 10 T SRAM permits bit interleaving with column-wise write access control, having differential read path, thus, improving reliability of the SRAM cell. The proposed circuit also restricts pseudoread problem, by allowing column-wise write in SRAM cell array. The simulation has been carried out on Cadence Virtuoso at 45nm technology node.
|Title of host publication||2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2018|
|Publication status||Published - 2019|
|Event||IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2018 - Chicago, United States|
Duration: 8 Oct 2018 → 10 Oct 2018
|Conference||IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2018|
|Abbreviated title||DFT 2018|
|Period||8/10/18 → 10/10/18|