5.5-V I/O in a 2.5-V 0.25-µm CMOS technology

Anne J. Annema, Govert J.G.M. Geelen, Peter C. de Jong

    Research output: Contribution to journalArticleAcademicpeer-review

    106 Citations (Scopus)
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    A robust high-voltage-tolerant I/O that does not need process options is presented, demonstrated on 5.5-V-tolerant I/O in a 2.5-V 0.25-µm CMOS technology. Circuit techniques limit oxide stress and hot-carrier degradation. Measurements on realized circuits, under accelerated stress conditions, indicate an extrapolated lifetime of hundreds of years for 5.5-V pad voltage swing, 2.2-V supply voltage. The shown concepts can easily be scaled toward newer processes or other interfacing voltages
    Original languageEnglish
    Pages (from-to)528-538
    Number of pages11
    JournalIEEE journal of solid-state circuits
    Issue number3
    Publication statusPublished - Mar 2001


    • IR-67625
    • CMOS integrated circuits
    • Buffer
    • I/O
    • Reliability
    • high-voltage techniques
    • EWI-14338


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