5.5-V I/O in a 2.5-V 0.25-µm CMOS technology

Anne J. Annema; Govert J.G.M. Geelen; Peter C. de Jong

doi:10.1109/4.910493

5.5-V I/O in a 2.5-V 0.25-µm CMOS technology

Anne J. Annema, Govert J.G.M. Geelen, Peter C. de Jong

Research output: Contribution to journal › Article › Academic › peer-review

109 Citations (Scopus)

46 Downloads (Pure)

Abstract

A robust high-voltage-tolerant I/O that does not need process options is presented, demonstrated on 5.5-V-tolerant I/O in a 2.5-V 0.25-µm CMOS technology. Circuit techniques limit oxide stress and hot-carrier degradation. Measurements on realized circuits, under accelerated stress conditions, indicate an extrapolated lifetime of hundreds of years for 5.5-V pad voltage swing, 2.2-V supply voltage. The shown concepts can easily be scaled toward newer processes or other interfacing voltages

Original language	English
Pages (from-to)	528-538
Number of pages	11
Journal	IEEE journal of solid-state circuits
Volume	36
Issue number	3
DOIs	https://doi.org/10.1109/4.910493
Publication status	Published - Mar 2001

Keywords

IR-67625
CMOS integrated circuits
Buffer
I/O
Reliability
high-voltage techniques
EWI-14338

Access to Document

10.1109/4.910493

Cite this

@article{b53e7ee877f24ba69b5030c20b2afed7,

title = "5.5-V I/O in a 2.5-V 0.25-µm CMOS technology",

abstract = "A robust high-voltage-tolerant I/O that does not need process options is presented, demonstrated on 5.5-V-tolerant I/O in a 2.5-V 0.25-µm CMOS technology. Circuit techniques limit oxide stress and hot-carrier degradation. Measurements on realized circuits, under accelerated stress conditions, indicate an extrapolated lifetime of hundreds of years for 5.5-V pad voltage swing, 2.2-V supply voltage. The shown concepts can easily be scaled toward newer processes or other interfacing voltages",

keywords = "IR-67625, CMOS integrated circuits, Buffer, I/O, Reliability, high-voltage techniques, EWI-14338",

author = "Annema, {Anne J.} and Geelen, {Govert J.G.M.} and {de Jong}, {Peter C.}",

year = "2001",

month = mar,

doi = "10.1109/4.910493",

language = "English",

volume = "36",

pages = "528--538",

journal = "IEEE journal of solid-state circuits",

issn = "0018-9200",

publisher = "IEEE",

number = "3",

}

TY - JOUR

T1 - 5.5-V I/O in a 2.5-V 0.25-µm CMOS technology

AU - Annema, Anne J.

AU - Geelen, Govert J.G.M.

AU - de Jong, Peter C.

PY - 2001/3

Y1 - 2001/3

N2 - A robust high-voltage-tolerant I/O that does not need process options is presented, demonstrated on 5.5-V-tolerant I/O in a 2.5-V 0.25-µm CMOS technology. Circuit techniques limit oxide stress and hot-carrier degradation. Measurements on realized circuits, under accelerated stress conditions, indicate an extrapolated lifetime of hundreds of years for 5.5-V pad voltage swing, 2.2-V supply voltage. The shown concepts can easily be scaled toward newer processes or other interfacing voltages

AB - A robust high-voltage-tolerant I/O that does not need process options is presented, demonstrated on 5.5-V-tolerant I/O in a 2.5-V 0.25-µm CMOS technology. Circuit techniques limit oxide stress and hot-carrier degradation. Measurements on realized circuits, under accelerated stress conditions, indicate an extrapolated lifetime of hundreds of years for 5.5-V pad voltage swing, 2.2-V supply voltage. The shown concepts can easily be scaled toward newer processes or other interfacing voltages

KW - IR-67625

KW - CMOS integrated circuits

KW - Buffer

KW - I/O

KW - Reliability

KW - high-voltage techniques

KW - EWI-14338

U2 - 10.1109/4.910493

DO - 10.1109/4.910493

M3 - Article

SN - 0018-9200

VL - 36

SP - 528

EP - 538

JO - IEEE journal of solid-state circuits

JF - IEEE journal of solid-state circuits

IS - 3

ER -

5.5-V I/O in a 2.5-V 0.25-µm CMOS technology

Abstract

Keywords

Access to Document

Fingerprint

Cite this