70 input, 20 nanosecond pattern classifier

P. Masa, P. Masa, K. Hoen, Klaas Hoen, Hans Wallinga

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    5 Citations (Scopus)
    48 Downloads (Pure)

    Abstract

    A CMOS neural network integrated circuit is discussed, which was designed for very high speed applications. This full-custom, mixed analog-digital chip implements a fully connected feedforward neural network with 70 inputs, 6 hidden layer neurons and one output neuron. The neurons perform inner product operation and have a sigmoid-like activation function. The 70 network inputs and the neural signal processing are analog, the synaptic weights are digitally programmable with 5 bit (4 bits+sign) precision. The synaptic weights are stored on on-chip static RAM cells. The combination of analog and digital techniques results in unique computing power with ease of use. Programming can easily be performed with the help of a spreadsheet or other suitable interface program from a PC. The resolution of the input signals is mainly determined by the signal to noise ratio which lies typically between 8-12 bits. Therefore the equivalent input bandwidth can be as high as 28-42 Gbits/second. The system is designed for very high speed vector classification and the feasibility of a single chip neural network photon trigger for nuclear research is shown. Because of the fully parallel architecture and the fast analog signal processing the network achieves unique computing performance and classifies up to 70 dimensional vectors within 20 nanoseconds, performing 20 billion (2×1010) multiply-and-add operations per second. The circuit occupies 10×9 mm2 silicon area with 1.5 μm CMOS process and dissipates only 1 W at 5 V supply.
    Original languageEnglish
    Title of host publicationProceedings of the IEEE International Conference on Neural Networks (Volume III, 3 of 7)
    Place of PublicationPiscataway, NJ, USA
    PublisherIEEE
    Pages1854-1859
    ISBN (Print)9780780319011
    DOIs
    Publication statusPublished - 28 Jun 1994
    Event1994 IEEE International Conference on Neural Networks, ICNN 1994 - Orlando, United States
    Duration: 27 Jun 19942 Jul 1994

    Publication series

    Name
    PublisherIEEE

    Conference

    Conference1994 IEEE International Conference on Neural Networks, ICNN 1994
    Abbreviated titleICNN
    CountryUnited States
    CityOrlando
    Period27/06/942/07/94

    Keywords

    • trigger circuits
    • very high speed integrated circuits
    • feedforward neural nets
    • detector circuits
    • mixed analogue-digital integrated circuits
    • high energy physics instrumentation computing
    • SRAM chips
    • CMOS integrated circuits
    • IR-71995
    • neural net architecture
    • neural chips
    • nuclear electronics
    • Pattern classification
    • METIS-113976

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