A 0.13um CMOS technology for low-voltage analogue applications

Y.V. Ponomarev, P.A. Stolk, A. van Brandenburg, C.J.J. Dachs, M. Kaiser, A.H. Montree, R. Roes, J. Schmitz, P.H. Woerlee

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    4 Citations (Scopus)


    Recent demand for battery-operated high-performance electronic products has stimulated a considerable effort towards the development of ultra low-voltage CMOS. We present here a novel approach based on an advanced lateral profiling technique coupled to gate work/unction engineering and show that this technology can rival the best SOI-based devices in speed (a record ring oscillator delay of 55ps at 0.45V supply voltage is measured). The performance of these devices for analogue applications is evaluated in detail to illustrate that the technology satisfy the analogue circuitry requirements, especially with the use of asymmetric source/drain configuration.

    Original languageEnglish
    Title of host publicationESSDERC 1999
    Subtitle of host publicationProceedings of the 29th European solid-state device research conference, Leuven, Belgium, 13-15 september
    EditorsR.P. Mertens, H. Grünbacher, H.E. Maes, G. Declerck
    Place of PublicationPiscataway, NJ
    PublisherIEEE Computer Society
    Number of pages4
    ISBN (Print)2-86332-245-1
    Publication statusPublished - 1 Jan 1999
    Event29th European Solid-State Device Research Conference, ESSDERC 1999 - Leuven, Belgium
    Duration: 13 Sep 199915 Sep 1999
    Conference number: 29


    Conference29th European Solid-State Device Research Conference, ESSDERC 1999
    Abbreviated titleESSDERC


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