Abstract
| Original language | English |
|---|---|
| Title of host publication | 2019 Symposium on VLSI Circuits |
| Subtitle of host publication | Digest of Technical Papers |
| Place of Publication | Kyoto, Japan |
| Publisher | IEEE |
| Pages | 74 |
| Number of pages | 75 |
| ISBN (Electronic) | 978-4-86348-720-8 |
| ISBN (Print) | 978-1-7281-0914-5 |
| DOIs | |
| Publication status | E-pub ahead of print/First online - 29 Jul 2019 |
| Event | 2019 IEEE Symposium on VLSI Circuits, VLSIC 2019 - Kyoto, Japan Duration: 9 Jun 2019 → 14 Jun 2019 |
Conference
| Conference | 2019 IEEE Symposium on VLSI Circuits, VLSIC 2019 |
|---|---|
| Abbreviated title | VLSIC 2019 |
| Country | Japan |
| City | Kyoto |
| Period | 9/06/19 → 14/06/19 |
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Keywords
- delay lines
- Capacitance
- Energy consumption
- Energy Efficiency
- Nonlinear distortion
- Computer architecture
Cite this
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A 0.2 - 8 MS/s 10b flexible SAR ADC Achieving 0.35 - 2.5 fJ/Conv-Step and using self-quenched dynamic bias comparator. / Bindra, Harijot Singh; Annema, Anne-Johan; Louwsma, Simon M.; Nauta, Bram .
2019 Symposium on VLSI Circuits: Digest of Technical Papers. Kyoto, Japan : IEEE, 2019. p. 74.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
TY - GEN
T1 - A 0.2 - 8 MS/s 10b flexible SAR ADC Achieving 0.35 - 2.5 fJ/Conv-Step and using self-quenched dynamic bias comparator
AU - Bindra, Harijot Singh
AU - Annema, Anne-Johan
AU - Louwsma, Simon M.
AU - Nauta, Bram
PY - 2019/7/29
Y1 - 2019/7/29
N2 - A 10b flexible SAR ADC is presented incorporating a selfquenched dynamic bias comparator and a self-triggered asynchronous delay line. The ADC is fabricated in 65nm CMOS, occupies 0.04mm2 and has an ENOB > 9bit and SFDR > 66dB for sampling rates from 0.2 to 8MS/s at supply voltages respectively from 0.7V to 1.3V with a Walden FoM from 0.35 to 2.5fJ/conv-step. Keywords: SAR ADC, flexible, Walden Figure-of-Merit, SNDR, dynamic bias.
AB - A 10b flexible SAR ADC is presented incorporating a selfquenched dynamic bias comparator and a self-triggered asynchronous delay line. The ADC is fabricated in 65nm CMOS, occupies 0.04mm2 and has an ENOB > 9bit and SFDR > 66dB for sampling rates from 0.2 to 8MS/s at supply voltages respectively from 0.7V to 1.3V with a Walden FoM from 0.35 to 2.5fJ/conv-step. Keywords: SAR ADC, flexible, Walden Figure-of-Merit, SNDR, dynamic bias.
KW - delay lines
KW - Capacitance
KW - Energy consumption
KW - Energy Efficiency
KW - Nonlinear distortion
KW - Computer architecture
U2 - 10.23919/VLSIC.2019.8778093
DO - 10.23919/VLSIC.2019.8778093
M3 - Conference contribution
SN - 978-1-7281-0914-5
SP - 74
BT - 2019 Symposium on VLSI Circuits
PB - IEEE
CY - Kyoto, Japan
ER -