A 0.2 - 8 MS/s 10b flexible SAR ADC Achieving 0.35 - 2.5 fJ/Conv-Step and using self-quenched dynamic bias comparator

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    Abstract

    A 10b flexible SAR ADC is presented incorporating a selfquenched dynamic bias comparator and a self-triggered asynchronous delay line. The ADC is fabricated in 65nm CMOS, occupies 0.04mm2 and has an ENOB > 9bit and SFDR > 66dB for sampling rates from 0.2 to 8MS/s at supply voltages respectively from 0.7V to 1.3V with a Walden FoM from 0.35 to 2.5fJ/conv-step. Keywords: SAR ADC, flexible, Walden Figure-of-Merit, SNDR, dynamic bias.
    Original languageEnglish
    Title of host publication2019 Symposium on VLSI Circuits
    Subtitle of host publicationDigest of Technical Papers
    Place of PublicationKyoto, Japan
    PublisherIEEE
    Pages74
    Number of pages75
    ISBN (Electronic)978-4-86348-720-8
    ISBN (Print)978-1-7281-0914-5
    DOIs
    Publication statusE-pub ahead of print/First online - 29 Jul 2019
    Event2019 IEEE Symposium on VLSI Circuits, VLSIC 2019 - Kyoto, Japan
    Duration: 9 Jun 201914 Jun 2019

    Conference

    Conference2019 IEEE Symposium on VLSI Circuits, VLSIC 2019
    Abbreviated titleVLSIC 2019
    CountryJapan
    CityKyoto
    Period9/06/1914/06/19

    Fingerprint

    Electric delay lines
    Sampling
    Electric potential

    Keywords

    • delay lines
    • Capacitance
    • Energy consumption
    • Energy Efficiency
    • Nonlinear distortion
    • Computer architecture

    Cite this

    Bindra, Harijot Singh ; Annema, Anne-Johan ; Louwsma, Simon M. ; Nauta, Bram . / A 0.2 - 8 MS/s 10b flexible SAR ADC Achieving 0.35 - 2.5 fJ/Conv-Step and using self-quenched dynamic bias comparator. 2019 Symposium on VLSI Circuits: Digest of Technical Papers. Kyoto, Japan : IEEE, 2019. pp. 74
    @inproceedings{11ab325f20fa4c129a1165b064b04d11,
    title = "A 0.2 - 8 MS/s 10b flexible SAR ADC Achieving 0.35 - 2.5 fJ/Conv-Step and using self-quenched dynamic bias comparator",
    abstract = "A 10b flexible SAR ADC is presented incorporating a selfquenched dynamic bias comparator and a self-triggered asynchronous delay line. The ADC is fabricated in 65nm CMOS, occupies 0.04mm2 and has an ENOB > 9bit and SFDR > 66dB for sampling rates from 0.2 to 8MS/s at supply voltages respectively from 0.7V to 1.3V with a Walden FoM from 0.35 to 2.5fJ/conv-step. Keywords: SAR ADC, flexible, Walden Figure-of-Merit, SNDR, dynamic bias.",
    keywords = "delay lines, Capacitance, Energy consumption, Energy Efficiency, Nonlinear distortion, Computer architecture",
    author = "Bindra, {Harijot Singh} and Anne-Johan Annema and Louwsma, {Simon M.} and Bram Nauta",
    year = "2019",
    month = "7",
    day = "29",
    doi = "10.23919/VLSIC.2019.8778093",
    language = "English",
    isbn = "978-1-7281-0914-5",
    pages = "74",
    booktitle = "2019 Symposium on VLSI Circuits",
    publisher = "IEEE",
    address = "United States",

    }

    Bindra, HS, Annema, A-J, Louwsma, SM & Nauta, B 2019, A 0.2 - 8 MS/s 10b flexible SAR ADC Achieving 0.35 - 2.5 fJ/Conv-Step and using self-quenched dynamic bias comparator. in 2019 Symposium on VLSI Circuits: Digest of Technical Papers. IEEE, Kyoto, Japan, pp. 74, 2019 IEEE Symposium on VLSI Circuits, VLSIC 2019, Kyoto, Japan, 9/06/19. https://doi.org/10.23919/VLSIC.2019.8778093

    A 0.2 - 8 MS/s 10b flexible SAR ADC Achieving 0.35 - 2.5 fJ/Conv-Step and using self-quenched dynamic bias comparator. / Bindra, Harijot Singh; Annema, Anne-Johan; Louwsma, Simon M.; Nauta, Bram .

    2019 Symposium on VLSI Circuits: Digest of Technical Papers. Kyoto, Japan : IEEE, 2019. p. 74.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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    AU - Bindra, Harijot Singh

    AU - Annema, Anne-Johan

    AU - Louwsma, Simon M.

    AU - Nauta, Bram

    PY - 2019/7/29

    Y1 - 2019/7/29

    N2 - A 10b flexible SAR ADC is presented incorporating a selfquenched dynamic bias comparator and a self-triggered asynchronous delay line. The ADC is fabricated in 65nm CMOS, occupies 0.04mm2 and has an ENOB > 9bit and SFDR > 66dB for sampling rates from 0.2 to 8MS/s at supply voltages respectively from 0.7V to 1.3V with a Walden FoM from 0.35 to 2.5fJ/conv-step. Keywords: SAR ADC, flexible, Walden Figure-of-Merit, SNDR, dynamic bias.

    AB - A 10b flexible SAR ADC is presented incorporating a selfquenched dynamic bias comparator and a self-triggered asynchronous delay line. The ADC is fabricated in 65nm CMOS, occupies 0.04mm2 and has an ENOB > 9bit and SFDR > 66dB for sampling rates from 0.2 to 8MS/s at supply voltages respectively from 0.7V to 1.3V with a Walden FoM from 0.35 to 2.5fJ/conv-step. Keywords: SAR ADC, flexible, Walden Figure-of-Merit, SNDR, dynamic bias.

    KW - delay lines

    KW - Capacitance

    KW - Energy consumption

    KW - Energy Efficiency

    KW - Nonlinear distortion

    KW - Computer architecture

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