@inproceedings{11ab325f20fa4c129a1165b064b04d11,
title = "A 0.2 - 8 MS/s 10b flexible SAR ADC Achieving 0.35 - 2.5 fJ/Conv-Step and using self-quenched dynamic bias comparator",
abstract = "A 10b flexible SAR ADC is presented incorporating a selfquenched dynamic bias comparator and a self-triggered asynchronous delay line. The ADC is fabricated in 65nm CMOS, occupies 0.04mm2 and has an ENOB > 9bit and SFDR > 66dB for sampling rates from 0.2 to 8MS/s at supply voltages respectively from 0.7V to 1.3V with a Walden FoM from 0.35 to 2.5fJ/conv-step.",
keywords = "Delay lines, Capacitance, Energy consumption, Energy efficiency, Nonlinear distortion, Computer architecture, SAR ADC, Flexible, Walden Figure-of-Merit, SNDR, Dynamic bias",
author = "Bindra, {Harijot Singh} and Anne-Johan Annema and Louwsma, {Simon M.} and Bram Nauta",
year = "2019",
month = jun,
day = "11",
doi = "10.23919/VLSIC.2019.8778093",
language = "English",
isbn = "978-1-7281-0914-5",
series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",
publisher = "IEEE",
pages = "C74--C75",
booktitle = "2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers",
address = "United States",
note = "2019 IEEE Symposium on VLSI Circuits, VLSIC 2019, VLSIC 2019 ; Conference date: 09-06-2019 Through 14-06-2019",
}