A 0.2 - 8 MS/s 10b flexible SAR ADC Achieving 0.35 - 2.5 fJ/Conv-Step and using self-quenched dynamic bias comparator

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    Abstract

    A 10b flexible SAR ADC is presented incorporating a selfquenched dynamic bias comparator and a self-triggered asynchronous delay line. The ADC is fabricated in 65nm CMOS, occupies 0.04mm2 and has an ENOB > 9bit and SFDR > 66dB for sampling rates from 0.2 to 8MS/s at supply voltages respectively from 0.7V to 1.3V with a Walden FoM from 0.35 to 2.5fJ/conv-step.
    Original languageEnglish
    Title of host publication2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers
    Subtitle of host publicationDigest of Technical Papers
    Place of PublicationPiscataway, NJ
    PublisherIEEE
    PagesC74-C75
    ISBN (Electronic)978-4-86348-718-5, 978-4-86348-720-8
    ISBN (Print)978-1-7281-0914-5
    DOIs
    Publication statusPublished - 11 Jun 2019
    Event2019 IEEE Symposium on VLSI Circuits, VLSIC 2019 - Kyoto, Japan
    Duration: 9 Jun 201914 Jun 2019

    Publication series

    NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers
    PublisherIEEE
    Volume2019
    ISSN (Print)2158-5601
    ISSN (Electronic)2158-5636

    Conference

    Conference2019 IEEE Symposium on VLSI Circuits, VLSIC 2019
    Abbreviated titleVLSIC 2019
    CountryJapan
    CityKyoto
    Period9/06/1914/06/19

    Keywords

    • Delay lines
    • Capacitance
    • Energy consumption
    • Energy efficiency
    • Nonlinear distortion
    • Computer architecture
    • SAR ADC
    • Flexible
    • Walden Figure-of-Merit
    • SNDR
    • Dynamic bias

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  • Cite this

    Bindra, H. S., Annema, A-J., Louwsma, S. M., & Nauta, B. (2019). A 0.2 - 8 MS/s 10b flexible SAR ADC Achieving 0.35 - 2.5 fJ/Conv-Step and using self-quenched dynamic bias comparator. In 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers: Digest of Technical Papers (pp. C74-C75). [8778093] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2019). Piscataway, NJ: IEEE. https://doi.org/10.23919/VLSIC.2019.8778093