A 0.2 - 8 MS/s 10b flexible SAR ADC Achieving 0.35 - 2.5 fJ/Conv-Step and using self-quenched dynamic bias comparator

Harijot Singh Bindra; Anne-Johan Annema; Simon M. Louwsma; Bram  Nauta

doi:10.23919/VLSIC.2019.8778093

A 0.2 - 8 MS/s 10b flexible SAR ADC Achieving 0.35 - 2.5 fJ/Conv-Step and using self-quenched dynamic bias comparator

Harijot Singh Bindra, Anne-Johan Annema, Simon M. Louwsma, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

10 Citations (Scopus)

333 Downloads (Pure)

Abstract

A 10b flexible SAR ADC is presented incorporating a selfquenched dynamic bias comparator and a self-triggered asynchronous delay line. The ADC is fabricated in 65nm CMOS, occupies 0.04mm2 and has an ENOB > 9bit and SFDR > 66dB for sampling rates from 0.2 to 8MS/s at supply voltages respectively from 0.7V to 1.3V with a Walden FoM from 0.35 to 2.5fJ/conv-step.

Original language	English
Title of host publication	2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers
Subtitle of host publication	Digest of Technical Papers
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	C74-C75
ISBN (Electronic)	978-4-86348-718-5, 978-4-86348-720-8
ISBN (Print)	978-1-7281-0914-5
DOIs	https://doi.org/10.23919/VLSIC.2019.8778093
Publication status	Published - 11 Jun 2019
Event	2019 IEEE Symposium on VLSI Circuits, VLSIC 2019 - Kyoto, Japan Duration: 9 Jun 2019 → 14 Jun 2019

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Publisher	IEEE
Volume	2019
ISSN (Print)	2158-5601
ISSN (Electronic)	2158-5636

Conference

Conference	2019 IEEE Symposium on VLSI Circuits, VLSIC 2019
Abbreviated title	VLSIC 2019
Country/Territory	Japan
City	Kyoto
Period	9/06/19 → 14/06/19

Keywords

Delay lines
Capacitance
Energy consumption
Energy efficiency
Nonlinear distortion
Computer architecture
SAR ADC
Flexible
Walden Figure-of-Merit
SNDR
Dynamic bias

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.23919/VLSIC.2019.8778093

Bindra VLSI 2019Accepted author version, 519 KB

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Bindra, H. S., Annema, A-J., Louwsma, S. M., & Nauta, B. (2019). A 0.2 - 8 MS/s 10b flexible SAR ADC Achieving 0.35 - 2.5 fJ/Conv-Step and using self-quenched dynamic bias comparator. In 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers: Digest of Technical Papers (pp. C74-C75). [8778093] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2019). IEEE. https://doi.org/10.23919/VLSIC.2019.8778093

Bindra, Harijot Singh ; Annema, Anne-Johan ; Louwsma, Simon M. et al. / A 0.2 - 8 MS/s 10b flexible SAR ADC Achieving 0.35 - 2.5 fJ/Conv-Step and using self-quenched dynamic bias comparator. 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers: Digest of Technical Papers. Piscataway, NJ : IEEE, 2019. pp. C74-C75 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

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abstract = "A 10b flexible SAR ADC is presented incorporating a selfquenched dynamic bias comparator and a self-triggered asynchronous delay line. The ADC is fabricated in 65nm CMOS, occupies 0.04mm2 and has an ENOB > 9bit and SFDR > 66dB for sampling rates from 0.2 to 8MS/s at supply voltages respectively from 0.7V to 1.3V with a Walden FoM from 0.35 to 2.5fJ/conv-step.",

keywords = "Delay lines, Capacitance, Energy consumption, Energy efficiency, Nonlinear distortion, Computer architecture, SAR ADC, Flexible, Walden Figure-of-Merit, SNDR, Dynamic bias",

author = "Bindra, {Harijot Singh} and Anne-Johan Annema and Louwsma, {Simon M.} and Bram Nauta",

year = "2019",

month = jun,

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doi = "10.23919/VLSIC.2019.8778093",

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Bindra, HS , Annema, A-J, Louwsma, SM & Nauta, B 2019, A 0.2 - 8 MS/s 10b flexible SAR ADC Achieving 0.35 - 2.5 fJ/Conv-Step and using self-quenched dynamic bias comparator. in 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers: Digest of Technical Papers., 8778093, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2019, IEEE, Piscataway, NJ, pp. C74-C75, 2019 IEEE Symposium on VLSI Circuits, VLSIC 2019, Kyoto, Japan, 9/06/19. https://doi.org/10.23919/VLSIC.2019.8778093

A 0.2 - 8 MS/s 10b flexible SAR ADC Achieving 0.35 - 2.5 fJ/Conv-Step and using self-quenched dynamic bias comparator. / Bindra, Harijot Singh ; Annema, Anne-Johan; Louwsma, Simon M. et al.
2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers: Digest of Technical Papers. Piscataway, NJ: IEEE, 2019. p. C74-C75 8778093 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AB - A 10b flexible SAR ADC is presented incorporating a selfquenched dynamic bias comparator and a self-triggered asynchronous delay line. The ADC is fabricated in 65nm CMOS, occupies 0.04mm2 and has an ENOB > 9bit and SFDR > 66dB for sampling rates from 0.2 to 8MS/s at supply voltages respectively from 0.7V to 1.3V with a Walden FoM from 0.35 to 2.5fJ/conv-step.

KW - Delay lines

KW - Capacitance

KW - Energy consumption

KW - Energy efficiency

KW - Nonlinear distortion

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KW - Walden Figure-of-Merit

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Bindra HS , Annema A-J, Louwsma SM, Nauta B. A 0.2 - 8 MS/s 10b flexible SAR ADC Achieving 0.35 - 2.5 fJ/Conv-Step and using self-quenched dynamic bias comparator. In 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers: Digest of Technical Papers. Piscataway, NJ: IEEE. 2019. p. C74-C75. 8778093. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.23919/VLSIC.2019.8778093

A 0.2 - 8 MS/s 10b flexible SAR ADC Achieving 0.35 - 2.5 fJ/Conv-Step and using self-quenched dynamic bias comparator

Abstract

Publication series

Conference

Keywords

UN SDGs

Access to Document

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