A 0.2-to-2.0GHz 65nm CMOS Receiver without LNA achieving >11dBm IIP3 and

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    Abstract

    Spurious-free dynamic range (SFDR) is a key specification of radio receivers and spectrum analyzers, characterizing the maximum distance between signal and noise+distortion. SFDR is limited by the linearity (intercept point IIP3 mostly, sometimes IIP2) and the noise floor. As receivers already have low noise figure (NF) there is more room for improving the SFDR by increasing the linearity. As there is a strong relation between distortion and voltage swing, it is challenging to maintain or even improve linearity intercept points in future CMOS processes with lower supply voltages. Circuits can be linearized with feedback but loop gain at RF is limited [1]. Moreover, after LNA gain, mixer linearity becomes even tougher. If the amplification is postponed to IF, much more loop gain is available to linearize the amplifier. This paper proposes such an LNA-less mixer-first receiver. By careful analysis and optimization of a passive mixer core [2,3] for low conversion loss and low noise folding it is shown that it is possible to realize IIP3≫11dBm and NF≪6.5dB, i.e. a remarkably high SFDR≫79dB in 1MHz bandwidth over a decade of RF frequencies.
    Original languageEnglish
    Title of host publicationIEEE International Solid-State Circuits Conference
    Place of PublicationPiscataway
    PublisherIEEE Computer Society
    Pages222-223
    Number of pages2
    ISBN (Print)978-1-4244-3458-9
    DOIs
    Publication statusPublished - 10 Jan 2009
    EventIEEE International Solid-State Circuits Conference, ISSCC 2009 - San Francisco, United States
    Duration: 8 Feb 200912 Feb 2009

    Conference

    ConferenceIEEE International Solid-State Circuits Conference, ISSCC 2009
    Abbreviated titleISSCC
    CountryUnited States
    CitySan Francisco
    Period8/02/0912/02/09

    Keywords

    • IR-65507
    • METIS-263871
    • EWI-15403

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    Soer, M. C. M., Klumperink, E. A. M., Ru, Z., van Vliet, F. E., & Nauta, B. (2009). A 0.2-to-2.0GHz 65nm CMOS Receiver without LNA achieving >11dBm IIP3 and. In IEEE International Solid-State Circuits Conference (pp. 222-223). Piscataway: IEEE Computer Society. https://doi.org/10.1109/ISSCC.2009.4977388