A 0.28pJ/b 2Gb/s/ch transceiver in 90nm CMOS for 10mm on-chip interconnects

E. Mensink, Daniel Schinkel, Eric A.M. Klumperink, Adrianus Johannes Maria van Tuijl, Bram Nauta

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    51 Citations (Scopus)
    108 Downloads (Pure)

    Abstract

    Abstract A low-swing transceiver for 10mm-long 0.54mum-wide on-chip interconnects is presented. A capacitive pre-emphasis transmitter lowers the power and increases the bandwidth. The receiver uses DFE with a power-efficient continuous-time feedback filter. The transceiver, fabricated in 1.2V 90nm CMOS, achieves 2Gb/s. It consumes 0.28pJ/b, which is 7times lower than earlier work
    Original languageEnglish
    Title of host publication2007 IEEE International Solid-State Circuits Conference (ISSCC)
    Place of PublicationPiscataway
    PublisherIEEE Computer Society Press
    Pages414-415
    Number of pages2
    ISBN (Print)1-4244-0852-0
    DOIs
    Publication statusPublished - 14 Feb 2007
    EventIEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco Marriott, San Francisco, United States
    Duration: 3 Feb 20077 Feb 2007

    Conference

    ConferenceIEEE International Solid-State Circuits Conference, ISSCC 2007
    Abbreviated titleISSCC
    CountryUnited States
    CitySan Francisco
    Period3/02/077/02/07

    Keywords

    • EWI-9992
    • IR-58151
    • METIS-245718

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