A 0.28pJ/b 2Gb/s/ch transceiver in 90nm CMOS for 10mm on-chip interconnects

E. Mensink; Daniel Schinkel; Eric A.M. Klumperink; Adrianus Johannes Maria van Tuijl; Bram Nauta

doi:10.1109/ISSCC.2007.373470

A 0.28pJ/b 2Gb/s/ch transceiver in 90nm CMOS for 10mm on-chip interconnects

E. Mensink, Daniel Schinkel, Eric A.M. Klumperink, Adrianus Johannes Maria van Tuijl, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

53 Citations (Scopus)

279 Downloads (Pure)

Abstract

Abstract A low-swing transceiver for 10mm-long 0.54mum-wide on-chip interconnects is presented. A capacitive pre-emphasis transmitter lowers the power and increases the bandwidth. The receiver uses DFE with a power-efficient continuous-time feedback filter. The transceiver, fabricated in 1.2V 90nm CMOS, achieves 2Gb/s. It consumes 0.28pJ/b, which is 7times lower than earlier work

Original language	English
Title of host publication	2007 IEEE International Solid-State Circuits Conference (ISSCC)
Place of Publication	Piscataway
Publisher	IEEE
Pages	414-415
Number of pages	2
ISBN (Print)	1-4244-0852-0
DOIs	https://doi.org/10.1109/ISSCC.2007.373470
Publication status	Published - 14 Feb 2007
Event	IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco Marriott, San Francisco, United States Duration: 3 Feb 2007 → 7 Feb 2007

Conference

Conference	IEEE International Solid-State Circuits Conference, ISSCC 2007
Abbreviated title	ISSCC
Country/Territory	United States
City	San Francisco
Period	3/02/07 → 7/02/07

Keywords

EWI-9992
IR-58151
METIS-245718

Access to Document

10.1109/ISSCC.2007.373470

0.28Final published version, 2.8 MB

Cite this

@inproceedings{98d186cda78d41da9b87235ef8397337,

title = "A 0.28pJ/b 2Gb/s/ch transceiver in 90nm CMOS for 10mm on-chip interconnects",

abstract = "Abstract A low-swing transceiver for 10mm-long 0.54mum-wide on-chip interconnects is presented. A capacitive pre-emphasis transmitter lowers the power and increases the bandwidth. The receiver uses DFE with a power-efficient continuous-time feedback filter. The transceiver, fabricated in 1.2V 90nm CMOS, achieves 2Gb/s. It consumes 0.28pJ/b, which is 7times lower than earlier work",

keywords = "EWI-9992, IR-58151, METIS-245718",

author = "E. Mensink and Daniel Schinkel and Klumperink, {Eric A.M.} and {van Tuijl}, {Adrianus Johannes Maria} and Bram Nauta",

year = "2007",

month = feb,

day = "14",

doi = "10.1109/ISSCC.2007.373470",

language = "English",

isbn = "1-4244-0852-0",

pages = "414--415",

booktitle = "2007 IEEE International Solid-State Circuits Conference (ISSCC)",

publisher = "IEEE",

address = "United States",

note = "IEEE International Solid-State Circuits Conference, ISSCC 2007, ISSCC ; Conference date: 03-02-2007 Through 07-02-2007",

}

Mensink, E, Schinkel, D, Klumperink, EAM, van Tuijl, AJM & Nauta, B 2007, A 0.28pJ/b 2Gb/s/ch transceiver in 90nm CMOS for 10mm on-chip interconnects. in 2007 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, Piscataway, pp. 414-415, IEEE International Solid-State Circuits Conference, ISSCC 2007, San Francisco, California, United States, 3/02/07. https://doi.org/10.1109/ISSCC.2007.373470

TY - GEN

T1 - A 0.28pJ/b 2Gb/s/ch transceiver in 90nm CMOS for 10mm on-chip interconnects

AU - Mensink, E.

AU - Schinkel, Daniel

AU - Klumperink, Eric A.M.

AU - van Tuijl, Adrianus Johannes Maria

AU - Nauta, Bram

PY - 2007/2/14

Y1 - 2007/2/14

N2 - Abstract A low-swing transceiver for 10mm-long 0.54mum-wide on-chip interconnects is presented. A capacitive pre-emphasis transmitter lowers the power and increases the bandwidth. The receiver uses DFE with a power-efficient continuous-time feedback filter. The transceiver, fabricated in 1.2V 90nm CMOS, achieves 2Gb/s. It consumes 0.28pJ/b, which is 7times lower than earlier work

AB - Abstract A low-swing transceiver for 10mm-long 0.54mum-wide on-chip interconnects is presented. A capacitive pre-emphasis transmitter lowers the power and increases the bandwidth. The receiver uses DFE with a power-efficient continuous-time feedback filter. The transceiver, fabricated in 1.2V 90nm CMOS, achieves 2Gb/s. It consumes 0.28pJ/b, which is 7times lower than earlier work

KW - EWI-9992

KW - IR-58151

KW - METIS-245718

U2 - 10.1109/ISSCC.2007.373470

DO - 10.1109/ISSCC.2007.373470

M3 - Conference contribution

SN - 1-4244-0852-0

SP - 414

EP - 415

BT - 2007 IEEE International Solid-State Circuits Conference (ISSCC)

PB - IEEE

CY - Piscataway

T2 - IEEE International Solid-State Circuits Conference, ISSCC 2007

Y2 - 3 February 2007 through 7 February 2007

ER -

A 0.28pJ/b 2Gb/s/ch transceiver in 90nm CMOS for 10mm on-chip interconnects

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Keywords

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