A 0.4–0.9 V Supply Voltage-Flexible Third-Order Passive ΔΣ Modulator With Switched-Capacitor Loop Filter Achieving 71.9 dB Peak SNDR at 4 MHz Bandwidth

This paper describes the design and implementation of a 4 MHz bandwidth 3rd-order Discrete-Time (DT) Passive Delta-Sigma Modulator (PΔΣM), which avoids the use of supply voltage-sensitive linear amplifiers. The Switched-Capacitor (SC) operation and amplifier-less nature of its loop filter render the proposed modulator highly supply voltage- and clock frequency-flexible. To explain our design choices, we investigate two key design challenges unique to PΔΣMs. Firstly, the noise criticality of the quantizer ADC due to the lack of (voltage) gain in the loop filter preceding it. Secondly, the inaccessibility of the readily synthesizable and highly frequency-selective loop filter frequency responses typically employed in ΔΣMs, caused by the absence of linear amplifiers. We show that the noise-power trade-off of the quantizer ADC in 1 bit PΔΣMs is the same as that of the first integrator amplifier in Active ΔΣM. Next,
we cover the suitability of several passive filters for use in PΔΣM loops. This leads to the selection of the voltage-sampled
Charge-Rotating IIR (CR-IIR) filter, for which we show ΔΣM-oriented design equations, on which we base the design of our 3rd-order DT PΔΣM. Measurement results on the resulting prototype PΔΣM, implemented in GlobalFoundries 22 nm FD-SOI CMOS, demonstrate that it achieves a 71.9 dB peak SNDR and 4 MHz bandwidth while consuming 4.4 mW from a 0.9 V supply and occupying 0.076mm2 of silicon area. The prototype PΔΣM continues to operate at a 2.25× reduced supply voltage of 0.4 V, albeit at a reduced bandwidth of 156.25 kHz, where it achieves a peak SNDR of 62 dB while consuming 37.8 μW