A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior

P. Veldhorst; George Goksun; Berry Buter; Maarten Vertregt; Anne J. Annema; Bram Nauta

doi:10.1109/ESSCIRC.2009.5326002

A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior

P. Veldhorst, George Goksun, Berry Buter, Maarten Vertregt, Anne J. Annema, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

8 Citations (Scopus)

155 Downloads (Pure)

Abstract

A 6-bit 1.2 Gs/s non-calibrated flash ADC in a standard 45nm CMOS process, that achieves 0.45pJ/conv-step at full Nyquist bandwidth, is presented. Power efficient operation is achieved by a full optimization of amplifier blocks, and by innovations in the comparator and encoding stage. The performance of a non-calibrated flash ADC is directly related to device properties; a scaling analysis of our ADC in and across CMOS technologies gives insight into the excellent usability of 45nm technology for AD converter design.

Original language	English
Title of host publication	Proceedings of the ESSCIRC 2009
Place of Publication	Piscataway
Publisher	IEEE
Pages	464-467
Number of pages	4
ISBN (Print)	978-1-4244-4353-6
DOIs	https://doi.org/10.1109/ESSCIRC.2009.5326002
Publication status	Published - 14 Sept 2009
Event	35th European Solid-State Circuits Conference, ESSCIRC 2009 - Athene, Greece Duration: 14 Sept 2009 → 18 Sept 2009 Conference number: 35

Conference

Conference	35th European Solid-State Circuits Conference, ESSCIRC 2009
Abbreviated title	ESSCIRC
Country/Territory	Greece
City	Athene
Period	14/09/09 → 18/09/09

Keywords

IR-70007
METIS-265787
Amplifiers
EWI-17419
comparators (circuits) radio access networks
Nyquist criterion
analogue-digital conversion
CMOS integrated circuits

Access to Document

10.1109/ESSCIRC.2009.5326002

Veldhorst_ESSCIRC_2009Final published version, 1.03 MB

Cite this

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title = "A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior",

abstract = "A 6-bit 1.2 Gs/s non-calibrated flash ADC in a standard 45nm CMOS process, that achieves 0.45pJ/conv-step at full Nyquist bandwidth, is presented. Power efficient operation is achieved by a full optimization of amplifier blocks, and by innovations in the comparator and encoding stage. The performance of a non-calibrated flash ADC is directly related to device properties; a scaling analysis of our ADC in and across CMOS technologies gives insight into the excellent usability of 45nm technology for AD converter design.",

keywords = "IR-70007, METIS-265787, Amplifiers, EWI-17419, comparators (circuits) radio access networks, Nyquist criterion, analogue-digital conversion, CMOS integrated circuits",

author = "P. Veldhorst and George Goksun and Berry Buter and Maarten Vertregt and Annema, {Anne J.} and Bram Nauta",

year = "2009",

month = sep,

day = "14",

doi = "10.1109/ESSCIRC.2009.5326002",

language = "English",

isbn = "978-1-4244-4353-6",

pages = "464--467",

booktitle = "Proceedings of the ESSCIRC 2009",

publisher = "IEEE",

address = "United States",

note = "35th European Solid-State Circuits Conference, ESSCIRC 2009, ESSCIRC ; Conference date: 14-09-2009 Through 18-09-2009",

}

Veldhorst, P, Goksun, G, Buter, B, Vertregt, M, Annema, AJ & Nauta, B 2009, A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior. in Proceedings of the ESSCIRC 2009. IEEE, Piscataway, pp. 464-467, 35th European Solid-State Circuits Conference, ESSCIRC 2009, Athene, Greece, 14/09/09. https://doi.org/10.1109/ESSCIRC.2009.5326002

TY - GEN

T1 - A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior

AU - Veldhorst, P.

AU - Goksun, George

AU - Buter, Berry

AU - Vertregt, Maarten

AU - Annema, Anne J.

AU - Nauta, Bram

N1 - Conference code: 35

PY - 2009/9/14

Y1 - 2009/9/14

N2 - A 6-bit 1.2 Gs/s non-calibrated flash ADC in a standard 45nm CMOS process, that achieves 0.45pJ/conv-step at full Nyquist bandwidth, is presented. Power efficient operation is achieved by a full optimization of amplifier blocks, and by innovations in the comparator and encoding stage. The performance of a non-calibrated flash ADC is directly related to device properties; a scaling analysis of our ADC in and across CMOS technologies gives insight into the excellent usability of 45nm technology for AD converter design.

AB - A 6-bit 1.2 Gs/s non-calibrated flash ADC in a standard 45nm CMOS process, that achieves 0.45pJ/conv-step at full Nyquist bandwidth, is presented. Power efficient operation is achieved by a full optimization of amplifier blocks, and by innovations in the comparator and encoding stage. The performance of a non-calibrated flash ADC is directly related to device properties; a scaling analysis of our ADC in and across CMOS technologies gives insight into the excellent usability of 45nm technology for AD converter design.

KW - IR-70007

KW - METIS-265787

KW - Amplifiers

KW - EWI-17419

KW - comparators (circuits) radio access networks

KW - Nyquist criterion

KW - analogue-digital conversion

KW - CMOS integrated circuits

U2 - 10.1109/ESSCIRC.2009.5326002

DO - 10.1109/ESSCIRC.2009.5326002

M3 - Conference contribution

SN - 978-1-4244-4353-6

SP - 464

EP - 467

BT - Proceedings of the ESSCIRC 2009

PB - IEEE

CY - Piscataway

T2 - 35th European Solid-State Circuits Conference, ESSCIRC 2009

Y2 - 14 September 2009 through 18 September 2009

ER -

A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior

Abstract

Conference

Keywords

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Cite this