A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s

Michiel van Elzakker; Ed van Tuijl; Paul Geraedts; Daniel Schinkel; Eric Klumperink; Bram Nauta

doi:10.1109/JSSC.2010.2043893

A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s

Michiel van Elzakker, Ed van Tuijl, Paul Geraedts, Daniel Schinkel, Eric Klumperink, Bram Nauta

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Abstract

This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115--225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step.

Original language	English
Pages (from-to)	1007-1015
Number of pages	9
Journal	IEEE journal of solid-state circuits
Volume	45
Issue number	5
DOIs	https://doi.org/10.1109/JSSC.2010.2043893
Publication status	Published - 1 May 2010

Keywords

Comparators (circuits)
Digital-analogue conversion
CMOS integrated circuits
Analogue-digital conversion
2023 OA procedure

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This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/JSSC.2010.2043893

ArticleFinal published version, 1.06 MBLicence: Taverne

Cite this

@article{8c2070d132294f0487e27d89ea67b1cd,

title = "A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s",

abstract = "This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115--225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step.",

keywords = "Comparators (circuits), Digital-analogue conversion, CMOS integrated circuits, Analogue-digital conversion, 2023 OA procedure",

author = "{van Elzakker}, Michiel and {van Tuijl}, Ed and Paul Geraedts and Daniel Schinkel and Eric Klumperink and Bram Nauta",

note = "10.1109/JSSC.2010.2043893 ",

year = "2010",

month = may,

day = "1",

doi = "10.1109/JSSC.2010.2043893",

language = "English",

volume = "45",

pages = "1007--1015",

journal = "IEEE journal of solid-state circuits",

issn = "0018-9200",

publisher = "IEEE",

number = "5",

}

TY - JOUR

T1 - A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s

AU - van Elzakker, Michiel

AU - van Tuijl, Ed

AU - Geraedts, Paul

AU - Schinkel, Daniel

AU - Klumperink, Eric

AU - Nauta, Bram

N1 - 10.1109/JSSC.2010.2043893

PY - 2010/5/1

Y1 - 2010/5/1

N2 - This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115--225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step.

AB - This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115--225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step.

KW - Comparators (circuits)

KW - Digital-analogue conversion

KW - CMOS integrated circuits

KW - Analogue-digital conversion

KW - 2023 OA procedure

U2 - 10.1109/JSSC.2010.2043893

DO - 10.1109/JSSC.2010.2043893

M3 - Article

SN - 0018-9200

VL - 45

SP - 1007

EP - 1015

JO - IEEE journal of solid-state circuits

JF - IEEE journal of solid-state circuits

IS - 5

ER -

A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s

Abstract

Keywords

UN SDGs

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