A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s

Michiel van Elzakker, Ed van Tuijl, Paul Geraedts, Daniel Schinkel, Eric Klumperink, Bram Nauta

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    This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115--225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step.
    Original languageEnglish
    Pages (from-to)1007-1015
    Number of pages9
    JournalIEEE journal of solid-state circuits
    Issue number5
    Publication statusPublished - 1 May 2010


    • Comparators (circuits)
    • Digital-analogue conversion
    • CMOS integrated circuits
    • Analogue-digital conversion
    • 2023 OA procedure


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