A 1.0-to-4.0GHz 65nm CMOS Four-Element Beamforming Receiver Using a Switched-Capacitor Vector Modulator with Approximate Sine Weighting via Charge Redistribution

M.C.M. Soer; Eric A.M. Klumperink; Bram Nauta; Frank Edward van Vliet

doi:10.1109/ISSCC.2011.5746221

A 1.0-to-4.0GHz 65nm CMOS Four-Element Beamforming Receiver Using a Switched-Capacitor Vector Modulator with Approximate Sine Weighting via Charge Redistribution

M.C.M. Soer, Eric A.M. Klumperink, Bram Nauta, Frank Edward van Vliet

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

20 Citations (Scopus)

6 Downloads (Pure)

Abstract

Phased-array receivers provide two major benefits over single-antenna receivers. Their signal-to-noise ratio (SNR) doubles for each doubling in the number of elements, resulting in extended range. Secondly, interferers can be rejected in the spatial domain for increased link robustness. These arrays can be implemented by phase shifting and summing the signals from antenna elements with uniform spacing. For accurate interference rejection, a phase shifter with uniform phase steps and constant amplitude is desired. Several types of continuous-time phase shifters have been published, e.g. using injection locking, phase selection and vector modulation. This paper proposes a phased-array receiver architecture with a discrete-time vector modulator that takes advantage of the high linearity and good matching of switched-capacitor circuits, which are highly compatible with advanced CMOS. A simple charge redistribution circuit is presented that performs a rational approximation of the sine and cosine needed for the vector modulator weights.

Original language	English
Title of host publication	IEEE International Solid-State Circuits Conference Digest of Technical Papers, ISSCC 2011
Place of Publication	Piscataway
Publisher	IEEE
Pages	64-66
Number of pages	3
ISBN (Print)	978-1-61284-303-2
DOIs	https://doi.org/10.1109/ISSCC.2011.5746221
Publication status	Published - 21 Feb 2011
Event	IEEE International Solid-State Circuits Conference, ISSCC 2011 - San Francisco, United States Duration: 20 Feb 2011 → 24 Feb 2011

Conference

Conference	IEEE International Solid-State Circuits Conference, ISSCC 2011
Abbreviated title	ISSCC
Country/Territory	United States
City	San Francisco
Period	20/02/11 → 24/02/11

Keywords

METIS-278755
Capacitors
CMOS integrated circuits
IR-77958
EWI-20420
Clocks
Phase modulation
Phase shifters
Receivers
Mixers

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10.1109/ISSCC.2011.5746221

Cite this

Soer, M. C. M., Klumperink, E. A. M., Nauta, B., & van Vliet, F. E. (2011). A 1.0-to-4.0GHz 65nm CMOS Four-Element Beamforming Receiver Using a Switched-Capacitor Vector Modulator with Approximate Sine Weighting via Charge Redistribution. In IEEE International Solid-State Circuits Conference Digest of Technical Papers, ISSCC 2011 (pp. 64-66). IEEE. https://doi.org/10.1109/ISSCC.2011.5746221

@inproceedings{b741cf9b519e43d8a44db19495bda6d6,

title = "A 1.0-to-4.0GHz 65nm CMOS Four-Element Beamforming Receiver Using a Switched-Capacitor Vector Modulator with Approximate Sine Weighting via Charge Redistribution",

abstract = "Phased-array receivers provide two major benefits over single-antenna receivers. Their signal-to-noise ratio (SNR) doubles for each doubling in the number of elements, resulting in extended range. Secondly, interferers can be rejected in the spatial domain for increased link robustness. These arrays can be implemented by phase shifting and summing the signals from antenna elements with uniform spacing. For accurate interference rejection, a phase shifter with uniform phase steps and constant amplitude is desired. Several types of continuous-time phase shifters have been published, e.g. using injection locking, phase selection and vector modulation. This paper proposes a phased-array receiver architecture with a discrete-time vector modulator that takes advantage of the high linearity and good matching of switched-capacitor circuits, which are highly compatible with advanced CMOS. A simple charge redistribution circuit is presented that performs a rational approximation of the sine and cosine needed for the vector modulator weights.",

keywords = "METIS-278755, Capacitors, CMOS integrated circuits, IR-77958, EWI-20420, Clocks, Phase modulation, Phase shifters, Receivers, Mixers",

author = "M.C.M. Soer and Klumperink, {Eric A.M.} and Bram Nauta and {van Vliet}, {Frank Edward}",

year = "2011",

month = feb,

day = "21",

doi = "10.1109/ISSCC.2011.5746221",

language = "English",

isbn = "978-1-61284-303-2",

pages = "64--66",

booktitle = "IEEE International Solid-State Circuits Conference Digest of Technical Papers, ISSCC 2011",

publisher = "IEEE",

note = "IEEE International Solid-State Circuits Conference, ISSCC 2011, ISSCC ; Conference date: 20-02-2011 Through 24-02-2011",

}

Soer, MCM, Klumperink, EAM , Nauta, B & van Vliet, FE 2011, A 1.0-to-4.0GHz 65nm CMOS Four-Element Beamforming Receiver Using a Switched-Capacitor Vector Modulator with Approximate Sine Weighting via Charge Redistribution. in IEEE International Solid-State Circuits Conference Digest of Technical Papers, ISSCC 2011. IEEE, Piscataway, pp. 64-66, IEEE International Solid-State Circuits Conference, ISSCC 2011, San Francisco, California, United States, 20/02/11. https://doi.org/10.1109/ISSCC.2011.5746221

A 1.0-to-4.0GHz 65nm CMOS Four-Element Beamforming Receiver Using a Switched-Capacitor Vector Modulator with Approximate Sine Weighting via Charge Redistribution. / Soer, M.C.M.; Klumperink, Eric A.M.; Nauta, Bram et al.

IEEE International Solid-State Circuits Conference Digest of Technical Papers, ISSCC 2011. Piscataway : IEEE, 2011. p. 64-66.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A 1.0-to-4.0GHz 65nm CMOS Four-Element Beamforming Receiver Using a Switched-Capacitor Vector Modulator with Approximate Sine Weighting via Charge Redistribution

AU - Soer, M.C.M.

AU - Klumperink, Eric A.M.

AU - Nauta, Bram

AU - van Vliet, Frank Edward

PY - 2011/2/21

Y1 - 2011/2/21

N2 - Phased-array receivers provide two major benefits over single-antenna receivers. Their signal-to-noise ratio (SNR) doubles for each doubling in the number of elements, resulting in extended range. Secondly, interferers can be rejected in the spatial domain for increased link robustness. These arrays can be implemented by phase shifting and summing the signals from antenna elements with uniform spacing. For accurate interference rejection, a phase shifter with uniform phase steps and constant amplitude is desired. Several types of continuous-time phase shifters have been published, e.g. using injection locking, phase selection and vector modulation. This paper proposes a phased-array receiver architecture with a discrete-time vector modulator that takes advantage of the high linearity and good matching of switched-capacitor circuits, which are highly compatible with advanced CMOS. A simple charge redistribution circuit is presented that performs a rational approximation of the sine and cosine needed for the vector modulator weights.

AB - Phased-array receivers provide two major benefits over single-antenna receivers. Their signal-to-noise ratio (SNR) doubles for each doubling in the number of elements, resulting in extended range. Secondly, interferers can be rejected in the spatial domain for increased link robustness. These arrays can be implemented by phase shifting and summing the signals from antenna elements with uniform spacing. For accurate interference rejection, a phase shifter with uniform phase steps and constant amplitude is desired. Several types of continuous-time phase shifters have been published, e.g. using injection locking, phase selection and vector modulation. This paper proposes a phased-array receiver architecture with a discrete-time vector modulator that takes advantage of the high linearity and good matching of switched-capacitor circuits, which are highly compatible with advanced CMOS. A simple charge redistribution circuit is presented that performs a rational approximation of the sine and cosine needed for the vector modulator weights.

KW - METIS-278755

KW - Capacitors

KW - CMOS integrated circuits

KW - IR-77958

KW - EWI-20420

KW - Clocks

KW - Phase modulation

KW - Phase shifters

KW - Receivers

KW - Mixers

U2 - 10.1109/ISSCC.2011.5746221

DO - 10.1109/ISSCC.2011.5746221

M3 - Conference contribution

SN - 978-1-61284-303-2

SP - 64

EP - 66

BT - IEEE International Solid-State Circuits Conference Digest of Technical Papers, ISSCC 2011

PB - IEEE

CY - Piscataway

T2 - IEEE International Solid-State Circuits Conference, ISSCC 2011

Y2 - 20 February 2011 through 24 February 2011

ER -

Soer MCM, Klumperink EAM , Nauta B , van Vliet FE. A 1.0-to-4.0GHz 65nm CMOS Four-Element Beamforming Receiver Using a Switched-Capacitor Vector Modulator with Approximate Sine Weighting via Charge Redistribution. In IEEE International Solid-State Circuits Conference Digest of Technical Papers, ISSCC 2011. Piscataway: IEEE. 2011. p. 64-66 doi: 10.1109/ISSCC.2011.5746221

A 1.0-to-4.0GHz 65nm CMOS Four-Element Beamforming Receiver Using a Switched-Capacitor Vector Modulator with Approximate Sine Weighting via Charge Redistribution

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Keywords

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