A 1.0-to-4.0GHz 65nm CMOS Four-Element Beamforming Receiver Using a Switched-Capacitor Vector Modulator with Approximate Sine Weighting via Charge Redistribution

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

17 Citations (Scopus)
6 Downloads (Pure)

Abstract

Phased-array receivers provide two major benefits over single-antenna receivers. Their signal-to-noise ratio (SNR) doubles for each doubling in the number of elements, resulting in extended range. Secondly, interferers can be rejected in the spatial domain for increased link robustness. These arrays can be implemented by phase shifting and summing the signals from antenna elements with uniform spacing. For accurate interference rejection, a phase shifter with uniform phase steps and constant amplitude is desired. Several types of continuous-time phase shifters have been published, e.g. using injection locking, phase selection and vector modulation. This paper proposes a phased-array receiver architecture with a discrete-time vector modulator that takes advantage of the high linearity and good matching of switched-capacitor circuits, which are highly compatible with advanced CMOS. A simple charge redistribution circuit is presented that performs a rational approximation of the sine and cosine needed for the vector modulator weights.
Original languageEnglish
Title of host publicationIEEE International Solid-State Circuits Conference Digest of Technical Papers, ISSCC 2011
Place of PublicationPiscataway
PublisherIEEE
Pages64-66
Number of pages3
ISBN (Print)978-1-61284-303-2
DOIs
Publication statusPublished - 21 Feb 2011
EventIEEE International Solid-State Circuits Conference, ISSCC 2011 - San Francisco, United States
Duration: 20 Feb 201124 Feb 2011

Conference

ConferenceIEEE International Solid-State Circuits Conference, ISSCC 2011
Abbreviated titleISSCC
CountryUnited States
CitySan Francisco
Period20/02/1124/02/11

Fingerprint

Beamforming
Modulators
Capacitors
Phase shifters
Antennas
Networks (circuits)
Signal to noise ratio
Modulation

Keywords

  • METIS-278755
  • Capacitors
  • CMOS integrated circuits
  • IR-77958
  • EWI-20420
  • Clocks
  • Phase modulation
  • Phase shifters
  • Receivers
  • Mixers

Cite this

@inproceedings{b741cf9b519e43d8a44db19495bda6d6,
title = "A 1.0-to-4.0GHz 65nm CMOS Four-Element Beamforming Receiver Using a Switched-Capacitor Vector Modulator with Approximate Sine Weighting via Charge Redistribution",
abstract = "Phased-array receivers provide two major benefits over single-antenna receivers. Their signal-to-noise ratio (SNR) doubles for each doubling in the number of elements, resulting in extended range. Secondly, interferers can be rejected in the spatial domain for increased link robustness. These arrays can be implemented by phase shifting and summing the signals from antenna elements with uniform spacing. For accurate interference rejection, a phase shifter with uniform phase steps and constant amplitude is desired. Several types of continuous-time phase shifters have been published, e.g. using injection locking, phase selection and vector modulation. This paper proposes a phased-array receiver architecture with a discrete-time vector modulator that takes advantage of the high linearity and good matching of switched-capacitor circuits, which are highly compatible with advanced CMOS. A simple charge redistribution circuit is presented that performs a rational approximation of the sine and cosine needed for the vector modulator weights.",
keywords = "METIS-278755, Capacitors, CMOS integrated circuits, IR-77958, EWI-20420, Clocks, Phase modulation, Phase shifters, Receivers, Mixers",
author = "M.C.M. Soer and Klumperink, {Eric A.M.} and Bram Nauta and {van Vliet}, {Frank Edward}",
year = "2011",
month = "2",
day = "21",
doi = "10.1109/ISSCC.2011.5746221",
language = "English",
isbn = "978-1-61284-303-2",
pages = "64--66",
booktitle = "IEEE International Solid-State Circuits Conference Digest of Technical Papers, ISSCC 2011",
publisher = "IEEE",
address = "United States",

}

Soer, MCM, Klumperink, EAM, Nauta, B & van Vliet, FE 2011, A 1.0-to-4.0GHz 65nm CMOS Four-Element Beamforming Receiver Using a Switched-Capacitor Vector Modulator with Approximate Sine Weighting via Charge Redistribution. in IEEE International Solid-State Circuits Conference Digest of Technical Papers, ISSCC 2011. IEEE, Piscataway, pp. 64-66, IEEE International Solid-State Circuits Conference, ISSCC 2011, San Francisco, United States, 20/02/11. https://doi.org/10.1109/ISSCC.2011.5746221

A 1.0-to-4.0GHz 65nm CMOS Four-Element Beamforming Receiver Using a Switched-Capacitor Vector Modulator with Approximate Sine Weighting via Charge Redistribution. / Soer, M.C.M.; Klumperink, Eric A.M.; Nauta, Bram; van Vliet, Frank Edward.

IEEE International Solid-State Circuits Conference Digest of Technical Papers, ISSCC 2011. Piscataway : IEEE, 2011. p. 64-66.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

TY - GEN

T1 - A 1.0-to-4.0GHz 65nm CMOS Four-Element Beamforming Receiver Using a Switched-Capacitor Vector Modulator with Approximate Sine Weighting via Charge Redistribution

AU - Soer, M.C.M.

AU - Klumperink, Eric A.M.

AU - Nauta, Bram

AU - van Vliet, Frank Edward

PY - 2011/2/21

Y1 - 2011/2/21

N2 - Phased-array receivers provide two major benefits over single-antenna receivers. Their signal-to-noise ratio (SNR) doubles for each doubling in the number of elements, resulting in extended range. Secondly, interferers can be rejected in the spatial domain for increased link robustness. These arrays can be implemented by phase shifting and summing the signals from antenna elements with uniform spacing. For accurate interference rejection, a phase shifter with uniform phase steps and constant amplitude is desired. Several types of continuous-time phase shifters have been published, e.g. using injection locking, phase selection and vector modulation. This paper proposes a phased-array receiver architecture with a discrete-time vector modulator that takes advantage of the high linearity and good matching of switched-capacitor circuits, which are highly compatible with advanced CMOS. A simple charge redistribution circuit is presented that performs a rational approximation of the sine and cosine needed for the vector modulator weights.

AB - Phased-array receivers provide two major benefits over single-antenna receivers. Their signal-to-noise ratio (SNR) doubles for each doubling in the number of elements, resulting in extended range. Secondly, interferers can be rejected in the spatial domain for increased link robustness. These arrays can be implemented by phase shifting and summing the signals from antenna elements with uniform spacing. For accurate interference rejection, a phase shifter with uniform phase steps and constant amplitude is desired. Several types of continuous-time phase shifters have been published, e.g. using injection locking, phase selection and vector modulation. This paper proposes a phased-array receiver architecture with a discrete-time vector modulator that takes advantage of the high linearity and good matching of switched-capacitor circuits, which are highly compatible with advanced CMOS. A simple charge redistribution circuit is presented that performs a rational approximation of the sine and cosine needed for the vector modulator weights.

KW - METIS-278755

KW - Capacitors

KW - CMOS integrated circuits

KW - IR-77958

KW - EWI-20420

KW - Clocks

KW - Phase modulation

KW - Phase shifters

KW - Receivers

KW - Mixers

U2 - 10.1109/ISSCC.2011.5746221

DO - 10.1109/ISSCC.2011.5746221

M3 - Conference contribution

SN - 978-1-61284-303-2

SP - 64

EP - 66

BT - IEEE International Solid-State Circuits Conference Digest of Technical Papers, ISSCC 2011

PB - IEEE

CY - Piscataway

ER -