A 100 – 800MHz 8-Path polyphase transmitter with mixer duty-cycle control achieving

Saqib Subhan, Eric A.M. Klumperink, Amir Ghaffari, Gerard J.M. Wienk, Bram Nauta

    Research output: Contribution to journalArticleAcademicpeer-review

    10 Citations (Scopus)
    615 Downloads (Pure)

    Abstract

    Radio transceivers capable of dynamic spectrum access require frequency agile transmitters with a clean output spectrum. High-Q filters are difficult to implement on chip and have limited tuning range. Transmitters with high linearity and broadband harmonic rejection can be more flexible and require less filtering. However, traditional Harmonic Rejection mixers suppress only a few harmonics. This paper presents an 8-path poly-phase transmitter, which exploits mixer-LO duty-cycle control and a tunable first-order RC low-pass filter to suppress ALL harmonics to below -40dBc. The optimum duty-cycle theoretically is 43.65% and a resolution of better than 0.1% is required to keep the spread in harmonic rejection within 1dB. We propose a simple monotonic duty-cycle control circuit and show by design equations and measurements that it achieves the required resolution over 3 octaves of frequency range. Also, analysis indicates that LO duty-cycle reduction compared to 50% improves power upconverter efficiency. A transmitter realized in 0.16■m CMOS works from 100-800MHz at a maximum single tone output power of 10.8dBm with an efficiency of 8.7%, outperforming previous designs. The OIP3 is >21dBm, while the LO leakage and image rejection is better than -45dBc.
    Original languageEnglish
    Pages (from-to)595-607
    Number of pages13
    JournalIEEE journal of solid-state circuits
    Volume49
    Issue number3
    DOIs
    Publication statusPublished - 1 Mar 2014

    Keywords

    • METIS-304064
    • IR-90515
    • EWI-24665
    • Cognitive radio
    • Duty-cycle control
    • Dynamic spectrum access
    • harmonic rejection
    • Mixer
    • Multipath
    • Polyphase
    • Power upconverter
    • Transmitter

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