A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist

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    Abstract

    A 9-bit 11GS/s current-steering (CS) digital-to-analog converter (DAC) is designed in 28nm FDSOI. The DAC uses two-times interleaving to suppress the effects of the main error mechanisms of CS DACs while its clock timing can be tuned by the back gates bias voltage of the multiplexer transistors. The DAC achieves higher than 50dB SFDR and less than -50dBc IM3 over Nyquist at a sampling rate of 11GS/s, occupying only 0.04mm2 and consuming 110mW from a single 1V supply.
    Original languageEnglish
    Title of host publication2014 Symposium on VLSI Circuits Digest of Technical Papers
    Place of PublicationPiscataway, NJ
    PublisherIEEE
    Pages1-2
    Number of pages2
    ISBN (Electronic)978-1-4799-3328-0
    ISBN (Print)978-1-4799-3327-3
    DOIs
    Publication statusPublished - 11 Jun 2014
    Event2014 IEEE Symposium on VLSI Circuits, VLSIC 2014 - Honolulu, United States
    Duration: 10 Jun 201413 Jun 2014

    Publication series

    NameSymposium on VLSI Circuits Digest of Technical Papers
    PublisherIEEE Press
    Volume2014
    ISSN (Print)2158-5601
    ISSN (Electronic)2158-5636

    Conference

    Conference2014 IEEE Symposium on VLSI Circuits, VLSIC 2014
    Abbreviated titleVLSIC
    CountryUnited States
    CityHonolulu
    Period10/06/1413/06/14

    Keywords

    • EWI-25147
    • IR-92149
    • METIS-306062

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