A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist

Erik Olieman; Anne-Johan Annema; Bram Nauta

doi:10.1109/VLSIC.2014.6858437

A 110mW, 0.04mm², 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist

Erik Olieman, Anne-Johan Annema, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

11 Citations (Scopus)

210 Downloads (Pure)

Abstract

A 9-bit 11GS/s current-steering (CS) digital-to-analog converter (DAC) is designed in 28nm FDSOI. The DAC uses two-times interleaving to suppress the effects of the main error mechanisms of CS DACs while its clock timing can be tuned by the back gates bias voltage of the multiplexer transistors. The DAC achieves higher than 50dB SFDR and less than -50dBc IM3 over Nyquist at a sampling rate of 11GS/s, occupying only 0.04mm2 and consuming 110mW from a single 1V supply.

Original language	English
Title of host publication	2014 Symposium on VLSI Circuits Digest of Technical Papers
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	1-2
Number of pages	2
ISBN (Electronic)	978-1-4799-3328-0
ISBN (Print)	978-1-4799-3327-3
DOIs	https://doi.org/10.1109/VLSIC.2014.6858437
Publication status	Published - 11 Jun 2014
Event	2014 IEEE Symposium on VLSI Circuits, VLSIC 2014 - Honolulu, United States Duration: 10 Jun 2014 → 13 Jun 2014

Publication series

Name	Symposium on VLSI Circuits Digest of Technical Papers
Publisher	IEEE Press
Volume	2014
ISSN (Print)	2158-5601
ISSN (Electronic)	2158-5636

Conference

Conference	2014 IEEE Symposium on VLSI Circuits, VLSIC 2014
Abbreviated title	VLSIC
Country/Territory	United States
City	Honolulu
Period	10/06/14 → 13/06/14

Keywords

EWI-25147
IR-92149
METIS-306062

Access to Document

10.1109/VLSIC.2014.6858437

Olieman2014interleavedAccepted author version, 213 KB

Cite this

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title = "A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist",

abstract = "A 9-bit 11GS/s current-steering (CS) digital-to-analog converter (DAC) is designed in 28nm FDSOI. The DAC uses two-times interleaving to suppress the effects of the main error mechanisms of CS DACs while its clock timing can be tuned by the back gates bias voltage of the multiplexer transistors. The DAC achieves higher than 50dB SFDR and less than -50dBc IM3 over Nyquist at a sampling rate of 11GS/s, occupying only 0.04mm2 and consuming 110mW from a single 1V supply.",

keywords = "EWI-25147, IR-92149, METIS-306062",

author = "Erik Olieman and Anne-Johan Annema and Bram Nauta",

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Olieman, E, Annema, A-J & Nauta, B 2014, A 110mW, 0.04mm², 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist. in 2014 Symposium on VLSI Circuits Digest of Technical Papers. Symposium on VLSI Circuits Digest of Technical Papers, vol. 2014, IEEE, Piscataway, NJ, pp. 1-2, 2014 IEEE Symposium on VLSI Circuits, VLSIC 2014, Honolulu, Hawaii, United States, 10/06/14. https://doi.org/10.1109/VLSIC.2014.6858437

A 110mW, 0.04mm², 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist. / Olieman, Erik; Annema, Anne-Johan ; Nauta, Bram.
2014 Symposium on VLSI Circuits Digest of Technical Papers. Piscataway, NJ: IEEE, 2014. p. 1-2 (Symposium on VLSI Circuits Digest of Technical Papers; Vol. 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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