A 12.8GS/s Sub-Sampling ADC Front-End With 38GHz Input Bandwidth and >39dB SNDR for 1 to 32GHz in 22nm FDSOI

Josef Heel; Harijot Singh Bindra; Simon Louwsma; Alessandro Dezzani; Bram Nauta

doi:10.1109/ISSCC49661.2025.10904786

A 12.8GS/s Sub-Sampling ADC Front-End With 38GHz Input Bandwidth and >39dB SNDR for 1 to 32GHz in 22nm FDSOI

Josef Heel, Harijot Singh Bindra, Simon Louwsma, Alessandro Dezzani, Bram Nauta

Integrated Circuit Design

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

The demand for higher data rates combined with the crowded wireless spectrum results in a trend towards millimeter-wave frequencies. RF-sampling architectures offer advantages in terms of flexibility, simplicity and robustness. However, presenting the ADC directly with tens of GHz at the input poses significant challenges especially to the front-end, leading to a demand for high-bandwidth-and fidelity implementations. This work targets RF-sampling of X-band to Ka-band frequencies while maximizing signal purity and a Nyquist bandwidth of 6.4GHz to allow flexibility and multi-channel reception, but minimizing system complexity and data-rate overhead. The focus is on the lower Ka-band around 27 to 31GHz used for high-throughput Earth-to-Satellite communication applications.

Original language	English
Title of host publication	A 12.8GS/s Sub-Sampling ADC Front-End With 38GHz Input Bandwidth and >39dB SNDR for 1 to 32GHz in 22nm FDSOI
Pages	76-78
Number of pages	3
ISBN (Electronic)	979-8-3315-4101-9
DOIs	https://doi.org/10.1109/ISSCC49661.2025.10904786
Publication status	Published - 6 Mar 2025
Event	IEEE International Solid-State Circuits Conference, ISSCC 2025 - San Francicso, United States Duration: 16 Feb 2025 → 20 Feb 2025

Conference

Conference	IEEE International Solid-State Circuits Conference, ISSCC 2025
Country/Territory	United States
City	San Francicso
Period	16/02/25 → 20/02/25

Keywords

2025 OA procedure
Silicon-on-insulator
bandwidth
Market research
robustness
Solid state circuits
complexity theory
ka-band
Millimeter wave communication
wireless communication

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10.1109/ISSCC49661.2025.10904786Licence: Other

Cite this

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title = "A 12.8GS/s Sub-Sampling ADC Front-End With 38GHz Input Bandwidth and >39dB SNDR for 1 to 32GHz in 22nm FDSOI",

abstract = "The demand for higher data rates combined with the crowded wireless spectrum results in a trend towards millimeter-wave frequencies. RF-sampling architectures offer advantages in terms of flexibility, simplicity and robustness. However, presenting the ADC directly with tens of GHz at the input poses significant challenges especially to the front-end, leading to a demand for high-bandwidth-and fidelity implementations. This work targets RF-sampling of X-band to Ka-band frequencies while maximizing signal purity and a Nyquist bandwidth of 6.4GHz to allow flexibility and multi-channel reception, but minimizing system complexity and data-rate overhead. The focus is on the lower Ka-band around 27 to 31GHz used for high-throughput Earth-to-Satellite communication applications.",

keywords = "2025 OA procedure, Silicon-on-insulator, bandwidth, Market research, robustness, Solid state circuits, complexity theory, ka-band, Millimeter wave communication, wireless communication",

author = "Josef Heel and Bindra, {Harijot Singh} and Simon Louwsma and Alessandro Dezzani and Bram Nauta",

year = "2025",

month = mar,

day = "6",

doi = "10.1109/ISSCC49661.2025.10904786",

language = "English",

pages = "76--78",

booktitle = "A 12.8GS/s Sub-Sampling ADC Front-End With 38GHz Input Bandwidth and >39dB SNDR for 1 to 32GHz in 22nm FDSOI",

note = "IEEE International Solid-State Circuits Conference, ISSCC 2025 ; Conference date: 16-02-2025 Through 20-02-2025",

}

Heel, J, Bindra, HS, Louwsma, S, Dezzani, A & Nauta, B 2025, A 12.8GS/s Sub-Sampling ADC Front-End With 38GHz Input Bandwidth and >39dB SNDR for 1 to 32GHz in 22nm FDSOI. in A 12.8GS/s Sub-Sampling ADC Front-End With 38GHz Input Bandwidth and >39dB SNDR for 1 to 32GHz in 22nm FDSOI. pp. 76-78, IEEE International Solid-State Circuits Conference, ISSCC 2025, San Francicso, California, United States, 16/02/25. https://doi.org/10.1109/ISSCC49661.2025.10904786

A 12.8GS/s Sub-Sampling ADC Front-End With 38GHz Input Bandwidth and >39dB SNDR for 1 to 32GHz in 22nm FDSOI. / Heel, Josef; Bindra, Harijot Singh; Louwsma, Simon et al.
A 12.8GS/s Sub-Sampling ADC Front-End With 38GHz Input Bandwidth and >39dB SNDR for 1 to 32GHz in 22nm FDSOI. 2025. p. 76-78.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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A 12.8GS/s Sub-Sampling ADC Front-End With 38GHz Input Bandwidth and >39dB SNDR for 1 to 32GHz in 22nm FDSOI

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