A 12b 1.7GS/s two-times interleaved DAC with

E. Olieman, Anne J. Annema, Bram Nauta, Ankur Bal, Pratap Narayan Singh

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

1 Citation (Scopus)
22 Downloads (Pure)

Abstract

A two-times interleaved DAC using only a single supply voltage in a standard 65nm CMOS technology is presented. The interleaving architecture suppresses most of the non-idealities commonly found in high-speed DACs. Spurs generated by the interleaved architecture are suppressed by a novel calibration algorithm. The design achieves IM3 levels below -62dB across Nyquist with a clock frequency of 1.7GHz. The circuit’s active area is 0.4mm2 and the power consumption is 70mW from a nominal 1.2V supply.
Original languageEnglish
Title of host publication2013 IEEE Asian Solid-State Circuits Conference
Place of PublicationUSA
PublisherIEEE
Pages81-84
Number of pages4
ISBN (Print)978-1-4799-0277-4
DOIs
Publication statusPublished - 11 Oct 2013
EventIEEE Asian Solid-State Circuits Conference, A-SSCC 2013 - Singapore, Singapore
Duration: 11 Nov 201313 Nov 2013

Conference

ConferenceIEEE Asian Solid-State Circuits Conference, A-SSCC 2013
Abbreviated titleA-SSCC
CountrySingapore
CitySingapore
Period11/11/1313/11/13

Fingerprint

Clocks
Electric power utilization
Calibration
Networks (circuits)
Electric potential

Keywords

  • EWI-24293
  • METIS-302635
  • IR-88764

Cite this

Olieman, E., Annema, A. J., Nauta, B., Bal, A., & Singh, P. N. (2013). A 12b 1.7GS/s two-times interleaved DAC with. In 2013 IEEE Asian Solid-State Circuits Conference (pp. 81-84). USA: IEEE. https://doi.org/10.1109/ASSCC.2013.6690987
Olieman, E. ; Annema, Anne J. ; Nauta, Bram ; Bal, Ankur ; Singh, Pratap Narayan. / A 12b 1.7GS/s two-times interleaved DAC with. 2013 IEEE Asian Solid-State Circuits Conference. USA : IEEE, 2013. pp. 81-84
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Olieman, E, Annema, AJ, Nauta, B, Bal, A & Singh, PN 2013, A 12b 1.7GS/s two-times interleaved DAC with. in 2013 IEEE Asian Solid-State Circuits Conference. IEEE, USA, pp. 81-84, IEEE Asian Solid-State Circuits Conference, A-SSCC 2013, Singapore, Singapore, 11/11/13. https://doi.org/10.1109/ASSCC.2013.6690987

A 12b 1.7GS/s two-times interleaved DAC with. / Olieman, E.; Annema, Anne J.; Nauta, Bram; Bal, Ankur; Singh, Pratap Narayan.

2013 IEEE Asian Solid-State Circuits Conference. USA : IEEE, 2013. p. 81-84.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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AB - A two-times interleaved DAC using only a single supply voltage in a standard 65nm CMOS technology is presented. The interleaving architecture suppresses most of the non-idealities commonly found in high-speed DACs. Spurs generated by the interleaved architecture are suppressed by a novel calibration algorithm. The design achieves IM3 levels below -62dB across Nyquist with a clock frequency of 1.7GHz. The circuit’s active area is 0.4mm2 and the power consumption is 70mW from a nominal 1.2V supply.

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Olieman E, Annema AJ, Nauta B, Bal A, Singh PN. A 12b 1.7GS/s two-times interleaved DAC with. In 2013 IEEE Asian Solid-State Circuits Conference. USA: IEEE. 2013. p. 81-84 https://doi.org/10.1109/ASSCC.2013.6690987