A 12b 1.7GS/s two-times interleaved DAC with

E. Olieman, Anne J. Annema, Bram Nauta, Ankur Bal, Pratap Narayan Singh

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    2 Citations (Scopus)
    62 Downloads (Pure)


    A two-times interleaved DAC using only a single supply voltage in a standard 65nm CMOS technology is presented. The interleaving architecture suppresses most of the non-idealities commonly found in high-speed DACs. Spurs generated by the interleaved architecture are suppressed by a novel calibration algorithm. The design achieves IM3 levels below -62dB across Nyquist with a clock frequency of 1.7GHz. The circuit’s active area is 0.4mm2 and the power consumption is 70mW from a nominal 1.2V supply.
    Original languageEnglish
    Title of host publication2013 IEEE Asian Solid-State Circuits Conference
    Place of PublicationUSA
    Number of pages4
    ISBN (Print)978-1-4799-0277-4
    Publication statusPublished - 11 Oct 2013
    EventIEEE Asian Solid-State Circuits Conference, A-SSCC 2013 - Singapore, Singapore
    Duration: 11 Nov 201313 Nov 2013


    ConferenceIEEE Asian Solid-State Circuits Conference, A-SSCC 2013
    Abbreviated titleA-SSCC


    • EWI-24293
    • METIS-302635
    • IR-88764

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