A 12b 1.7GS/s two-times interleaved DAC with

E. Olieman; Anne J. Annema; Bram Nauta; Ankur Bal; Pratap Narayan Singh

doi:10.1109/ASSCC.2013.6690987

A 12b 1.7GS/s two-times interleaved DAC with

E. Olieman
, Anne J. Annema
, Bram Nauta
, Ankur Bal
, Pratap Narayan Singh

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

7 Citations (Scopus)

372 Downloads (Pure)

Abstract

A two-times interleaved DAC using only a single supply voltage in a standard 65nm CMOS technology is presented. The interleaving architecture suppresses most of the non-idealities commonly found in high-speed DACs. Spurs generated by the interleaved architecture are suppressed by a novel calibration algorithm. The design achieves IM3 levels below -62dB across Nyquist with a clock frequency of 1.7GHz. The circuit’s active area is 0.4mm2 and the power consumption is 70mW from a nominal 1.2V supply.

Original language	English
Title of host publication	2013 IEEE Asian Solid-State Circuits Conference
Place of Publication	USA
Publisher	IEEE
Pages	81-84
Number of pages	4
ISBN (Print)	978-1-4799-0277-4
DOIs	https://doi.org/10.1109/ASSCC.2013.6690987
Publication status	Published - 11 Oct 2013
Event	IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 - Singapore, Singapore Duration: 11 Nov 2013 → 13 Nov 2013

Conference

Conference	IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
Abbreviated title	A-SSCC
Country/Territory	Singapore
City	Singapore
Period	11/11/13 → 13/11/13

Keywords

EWI-24293
METIS-302635
IR-88764

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10.1109/ASSCC.2013.6690987

E._Olieman_ASSCC_2013Accepted author version, 831 KB

Cite this

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title = "A 12b 1.7GS/s two-times interleaved DAC with",

abstract = "A two-times interleaved DAC using only a single supply voltage in a standard 65nm CMOS technology is presented. The interleaving architecture suppresses most of the non-idealities commonly found in high-speed DACs. Spurs generated by the interleaved architecture are suppressed by a novel calibration algorithm. The design achieves IM3 levels below -62dB across Nyquist with a clock frequency of 1.7GHz. The circuit{\textquoteright}s active area is 0.4mm2 and the power consumption is 70mW from a nominal 1.2V supply.",

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author = "E. Olieman and Annema, \{Anne J.\} and Bram Nauta and Ankur Bal and Singh, \{Pratap Narayan\}",

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AB - A two-times interleaved DAC using only a single supply voltage in a standard 65nm CMOS technology is presented. The interleaving architecture suppresses most of the non-idealities commonly found in high-speed DACs. Spurs generated by the interleaved architecture are suppressed by a novel calibration algorithm. The design achieves IM3 levels below -62dB across Nyquist with a clock frequency of 1.7GHz. The circuit’s active area is 0.4mm2 and the power consumption is 70mW from a nominal 1.2V supply.

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Y2 - 11 November 2013 through 13 November 2013

ER -

A 12b 1.7GS/s two-times interleaved DAC with

Abstract

Conference

Keywords

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