A 12GHz 210fs 6mW digital PLL with sub-sampling binary phase detector and voltage-time modulated DCO

Z. Ru; P. Geraedts; E. Klumperink; X. He; B. Nauta

A 12GHz 210fs 6mW digital PLL with sub-sampling binary phase detector and voltage-time modulated DCO

Z. Ru, P. Geraedts, E. Klumperink, X. He, B. Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

27 Citations (Scopus)

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Abstract

An integer-N digital PLL architecture is presented that simplifies the critical phase path using a sub-sampling binary (bang-bang) phase detector. Two power-efficient techniques are presented that can reduce DCO frequency tuning step by voltage-domain and time-domain (pulse-width) modulating the DCO LSB varactors. Measurement shows 210fs RMS jitter at 11.8GHz DCO frequency and 6mW power.

Original language	English
Title of host publication	Symposium on VLSI Circuits, VLSIC 2013
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	194-195
Number of pages	2
ISBN (Electronic)	978-4-86348-348-4
ISBN (Print)	978-1-4673-5531-5
Publication status	Published - 14 Jun 2013
Event	2013 IEEE Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan Duration: 12 Jun 2013 → 14 Jun 2013

Conference

Conference	2013 IEEE Symposium on VLSI Circuits, VLSIC 2013
Abbreviated title	VLSIC
Country/Territory	Japan
City	Kyoto
Period	12/06/13 → 14/06/13

Keywords

Frequency modulation
Phase Noise
IR-88759
Detectors
METIS-302530
Capacitors
EWI-23519
Phase locked loops
Jitter

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Ru2013digitalAccepted author version, 417 KB

http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6578659

Cite this

@inproceedings{98e67d6a7d744e4d968d1876c92fc12d,

title = "A 12GHz 210fs 6mW digital PLL with sub-sampling binary phase detector and voltage-time modulated DCO",

abstract = "An integer-N digital PLL architecture is presented that simplifies the critical phase path using a sub-sampling binary (bang-bang) phase detector. Two power-efficient techniques are presented that can reduce DCO frequency tuning step by voltage-domain and time-domain (pulse-width) modulating the DCO LSB varactors. Measurement shows 210fs RMS jitter at 11.8GHz DCO frequency and 6mW power.",

keywords = "Frequency modulation, Phase Noise, IR-88759, Detectors, METIS-302530, Capacitors, EWI-23519, Phase locked loops, Jitter",

author = "Z. Ru and P. Geraedts and E. Klumperink and X. He and B. Nauta",

note = "eemcs-eprint-23519 ; 2013 IEEE Symposium on VLSI Circuits, VLSIC 2013, VLSIC ; Conference date: 12-06-2013 Through 14-06-2013",

year = "2013",

month = jun,

day = "14",

language = "English",

isbn = "978-1-4673-5531-5",

pages = "194--195",

booktitle = "Symposium on VLSI Circuits, VLSIC 2013",

publisher = "IEEE",

address = "United States",

}

Ru, Z, Geraedts, P, Klumperink, E, He, X & Nauta, B 2013, A 12GHz 210fs 6mW digital PLL with sub-sampling binary phase detector and voltage-time modulated DCO. in Symposium on VLSI Circuits, VLSIC 2013. IEEE, Piscataway, NJ, pp. 194-195, 2013 IEEE Symposium on VLSI Circuits, VLSIC 2013, Kyoto, Japan, 12/06/13. <http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6578659>

TY - GEN

T1 - A 12GHz 210fs 6mW digital PLL with sub-sampling binary phase detector and voltage-time modulated DCO

AU - Ru, Z.

AU - Geraedts, P.

AU - Klumperink, E.

AU - He, X.

AU - Nauta, B.

N1 - eemcs-eprint-23519

PY - 2013/6/14

Y1 - 2013/6/14

N2 - An integer-N digital PLL architecture is presented that simplifies the critical phase path using a sub-sampling binary (bang-bang) phase detector. Two power-efficient techniques are presented that can reduce DCO frequency tuning step by voltage-domain and time-domain (pulse-width) modulating the DCO LSB varactors. Measurement shows 210fs RMS jitter at 11.8GHz DCO frequency and 6mW power.

AB - An integer-N digital PLL architecture is presented that simplifies the critical phase path using a sub-sampling binary (bang-bang) phase detector. Two power-efficient techniques are presented that can reduce DCO frequency tuning step by voltage-domain and time-domain (pulse-width) modulating the DCO LSB varactors. Measurement shows 210fs RMS jitter at 11.8GHz DCO frequency and 6mW power.

KW - Frequency modulation

KW - Phase Noise

KW - IR-88759

KW - Detectors

KW - METIS-302530

KW - Capacitors

KW - EWI-23519

KW - Phase locked loops

KW - Jitter

M3 - Conference contribution

SN - 978-1-4673-5531-5

SP - 194

EP - 195

BT - Symposium on VLSI Circuits, VLSIC 2013

PB - IEEE

CY - Piscataway, NJ

T2 - 2013 IEEE Symposium on VLSI Circuits, VLSIC 2013

Y2 - 12 June 2013 through 14 June 2013

ER -

A 12GHz 210fs 6mW digital PLL with sub-sampling binary phase detector and voltage-time modulated DCO

Abstract

Conference

Keywords

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