A 12GHz 210fs 6mW digital PLL with sub-sampling binary phase detector and voltage-time modulated DCO

Z. Ru, P. Geraedts, E. Klumperink, X. He, B. Nauta

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    19 Citations (Scopus)
    394 Downloads (Pure)

    Abstract

    An integer-N digital PLL architecture is presented that simplifies the critical phase path using a sub-sampling binary (bang-bang) phase detector. Two power-efficient techniques are presented that can reduce DCO frequency tuning step by voltage-domain and time-domain (pulse-width) modulating the DCO LSB varactors. Measurement shows 210fs RMS jitter at 11.8GHz DCO frequency and 6mW power.
    Original languageEnglish
    Title of host publicationSymposium on VLSI Circuits, VLSIC 2013
    Place of PublicationPiscataway, NJ
    PublisherIEEE
    Pages194-195
    Number of pages2
    ISBN (Electronic)978-4-86348-348-4
    ISBN (Print)978-1-4673-5531-5
    Publication statusPublished - 14 Jun 2013
    Event2013 IEEE Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan
    Duration: 12 Jun 201314 Jun 2013

    Conference

    Conference2013 IEEE Symposium on VLSI Circuits, VLSIC 2013
    Abbreviated titleVLSIC
    CountryJapan
    CityKyoto
    Period12/06/1314/06/13

    Keywords

    • Frequency modulation
    • Phase Noise
    • IR-88759
    • Detectors
    • METIS-302530
    • Capacitors
    • EWI-23519
    • Phase locked loops
    • Jitter

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