A 1.2V 10μW NPN-Based Temperature Sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3s) from -70°C to 125°C

F. Sebastiano; L.J. Breems; K.A.A. Makinwa; S. Drago; D.M.W. Leenaerts; Bram Nauta

doi:10.1109/ISSCC.2010.5433895

A 1.2V 10μW NPN-Based Temperature Sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3s) from -70°C to 125°C

F. Sebastiano, L.J. Breems, K.A.A. Makinwa, S. Drago, D.M.W. Leenaerts, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

This paper describes a temperature sensor realized in a 65nm CMOS process with a batch-calibrated inaccuracy of ±0.5°C (3σ) and a trimmed inaccuracy of ±0.2°C (3σ) from –70°C to 125°C. This represents a 10-fold improvement in accuracy compared to other deep-submicron temperature sensors [1,2], and is comparable with that of state-of-the-art sensors implemented in larger-featuresize processes [3,4]. The sensor draws 8.3μA from a 1.2V supply and occupies an area of 0.1mm2, which is 45 times less than that of sensors with comparable accuracy [3,4]. These advances are enabled by the use of NPN transistors as sensing elements, the use of dynamic techniques i.e. correlated double sampling (CDS) and dynamic element matching (DEM), and a single room-temperature trim.

Original language	Undefined
Title of host publication	Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 2010 IEEE International
Place of Publication	Piscataway
Publisher	IEEE
Pages	312-313
Number of pages	2
ISBN (Print)	978-1-4244-6033-5
DOIs	https://doi.org/10.1109/ISSCC.2010.5433895
Publication status	Published - 7 Feb 2010
Event	IEEE International Solid-State Circuits Conference, ISSCC 2010 - San Francisco, United States Duration: 7 Feb 2010 → 11 Feb 2010

Publication series

Name
Publisher	IEEE Press
ISSN (Print)	0193-6530

Conference

Conference	IEEE International Solid-State Circuits Conference, ISSCC 2010
Abbreviated title	ISSCC
Country/Territory	United States
City	San Francisco
Period	7/02/10 → 11/02/10

Keywords

METIS-270915
EWI-18149
IR-72402

Access to Document

10.1109/ISSCC.2010.5433895

Sebastiano,_F._IEEE_ISSCC_2010Final published version, 4.11 MB

Cite this

Sebastiano, F., Breems, L. J., Makinwa, K. A. A., Drago, S., Leenaerts, D. M. W., & Nauta, B. (2010). A 1.2V 10μW NPN-Based Temperature Sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3s) from -70°C to 125°C. In Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 2010 IEEE International (pp. 312-313). [10.1109/ISSCC.2010.5433895] IEEE. https://doi.org/10.1109/ISSCC.2010.5433895

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abstract = "This paper describes a temperature sensor realized in a 65nm CMOS process with a batch-calibrated inaccuracy of ±0.5°C (3σ) and a trimmed inaccuracy of ±0.2°C (3σ) from –70°C to 125°C. This represents a 10-fold improvement in accuracy compared to other deep-submicron temperature sensors [1,2], and is comparable with that of state-of-the-art sensors implemented in larger-featuresize processes [3,4]. The sensor draws 8.3μA from a 1.2V supply and occupies an area of 0.1mm2, which is 45 times less than that of sensors with comparable accuracy [3,4]. These advances are enabled by the use of NPN transistors as sensing elements, the use of dynamic techniques i.e. correlated double sampling (CDS) and dynamic element matching (DEM), and a single room-temperature trim.",

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Sebastiano, F, Breems, LJ, Makinwa, KAA, Drago, S, Leenaerts, DMW & Nauta, B 2010, A 1.2V 10μW NPN-Based Temperature Sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3s) from -70°C to 125°C. in Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 2010 IEEE International., 10.1109/ISSCC.2010.5433895, IEEE, Piscataway, pp. 312-313, IEEE International Solid-State Circuits Conference, ISSCC 2010, San Francisco, California, United States, 7/02/10. https://doi.org/10.1109/ISSCC.2010.5433895

A 1.2V 10μW NPN-Based Temperature Sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3s) from -70°C to 125°C. / Sebastiano, F.; Breems, L.J.; Makinwa, K.A.A. et al.

Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 2010 IEEE International. Piscataway : IEEE, 2010. p. 312-313 10.1109/ISSCC.2010.5433895.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - Nauta, Bram

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AB - This paper describes a temperature sensor realized in a 65nm CMOS process with a batch-calibrated inaccuracy of ±0.5°C (3σ) and a trimmed inaccuracy of ±0.2°C (3σ) from –70°C to 125°C. This represents a 10-fold improvement in accuracy compared to other deep-submicron temperature sensors [1,2], and is comparable with that of state-of-the-art sensors implemented in larger-featuresize processes [3,4]. The sensor draws 8.3μA from a 1.2V supply and occupies an area of 0.1mm2, which is 45 times less than that of sensors with comparable accuracy [3,4]. These advances are enabled by the use of NPN transistors as sensing elements, the use of dynamic techniques i.e. correlated double sampling (CDS) and dynamic element matching (DEM), and a single room-temperature trim.

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BT - Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 2010 IEEE International

PB - IEEE

CY - Piscataway

Y2 - 7 February 2010 through 11 February 2010

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Sebastiano F, Breems LJ, Makinwa KAA, Drago S, Leenaerts DMW, Nauta B. A 1.2V 10μW NPN-Based Temperature Sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3s) from -70°C to 125°C. In Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 2010 IEEE International. Piscataway: IEEE. 2010. p. 312-313. 10.1109/ISSCC.2010.5433895 doi: 10.1109/ISSCC.2010.5433895