This paper describes a temperature sensor realized in a 65nm CMOS process with a batch-calibrated inaccuracy of ±0.5°C (3σ) and a trimmed inaccuracy of ±0.2°C (3σ) from –70°C to 125°C. This represents a 10-fold improvement in
accuracy compared to other deep-submicron temperature sensors [1,2], and is comparable with that of state-of-the-art sensors implemented in larger-featuresize
processes [3,4]. The sensor draws 8.3μA from a 1.2V supply and occupies an area of 0.1mm2, which is 45 times less than that of sensors with comparable accuracy [3,4]. These advances are enabled by the use of NPN transistors as
sensing elements, the use of dynamic techniques i.e. correlated double sampling (CDS) and dynamic element matching (DEM), and a single room-temperature trim.
|Conference||IEEE International Solid-State Circuits Conference, ISSCC 2010|
|Period||7/02/10 → 11/02/10|