A 1.35 GS/s, 10b, 175 mW time-interleaved AD converter in 0.13 µm CMOS

S.M. Louwsma, Adrianus Johannes Maria van Tuijl, M. Vertregt, Bram Nauta

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    21 Citations (Scopus)
    51 Downloads (Pure)

    Abstract

    A time-interleaved ADC is presented with 16 channels, each consisting of two Successive Approximation (SA) ADCs in a pipeline configuration. Three techniques are presented to increase the speed of an SA-ADC. Single channel performance is 6.9 ENOB at an input frequency of 4 GHz. Multi-channel performance is 7.7 ENOB at 1.35 GS/s with an ERBW of 1 GHz and a FoM of 0.6 pJ/conversion-step. Keywords: ADC, SAR, SA-ADC, time-interleaved, T/H.
    Original languageEnglish
    Title of host publication2007 IEEE Symposium on VLSI Circuits
    Place of PublicationPiscataway
    PublisherIEEE Computer Society Press
    Pages62-63
    Number of pages2
    ISBN (Print)978-4-900784-04-8
    DOIs
    Publication statusPublished - 12 Jun 2007
    Event2007 IEEE Symposium on VLSI Circuits, VLSIC 2007 - Rihga Royal Hotel, Kyoto, Japan
    Duration: 14 Jun 200716 Jun 2007

    Conference

    Conference2007 IEEE Symposium on VLSI Circuits, VLSIC 2007
    Abbreviated titleVLSIC
    CountryJapan
    CityKyoto
    Period14/06/0716/06/07

    Keywords

    • EWI-10882
    • IR-64287
    • METIS-245725

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    Louwsma, S. M., van Tuijl, A. J. M., Vertregt, M., & Nauta, B. (2007). A 1.35 GS/s, 10b, 175 mW time-interleaved AD converter in 0.13 µm CMOS. In 2007 IEEE Symposium on VLSI Circuits (pp. 62-63). Piscataway: IEEE Computer Society Press. https://doi.org/10.1109/VLSIC.2007.4342766