A time-interleaved ADC is presented with 16 channels, each consisting of a track-and-hold (T&H) and two successive approximation (SA) ADCs in a pipeline configuration to combine a high sample rate with good power efficiency. The single-sided overrange architecture achieves a 25% higher power efficiency of the SA-ADC compared with the conventional overrange architecture, and look-ahead logic is used to minimize logic delay in the SA-ADC. For the T&H, three techniques are presented enabling a high bandwidth and linearity and good timing alignment. Single channel performance of the ADC is 6.9 ENOB at an input frequency of 4 GHz. Multichannel performance is 7.7 ENOB at 1.35 GS/s with an ERBW of 1 GHz. The FoM of the complete ADC including T&H is 0.6 pJ per conversion step. An improved version is presented as well and achieves an SNDR of 8.6 ENOB for low sample rates, and, with increased supply voltage, it reaches a sample rate of 1.8 GS/s with 7.9 ENOB at low input frequencies and an ERBW of 1 GHz. At fin = 3.6 GHz, the SNDR is still 6.5 ENOB, and total timing error including jitter is 0.4 ps rms.
- ICD-HIGH SPEED AD-CONVERTER DESIGN IN CMOS
Louwsma, S. M., van Tuijl, A. J. M., Vertregt, M., & Nauta, B. (2008). A 1.35 GS/s, 10b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS. IEEE journal of solid-state circuits, 43(302/4), 778-786. [10.1109/JSSC.2008.917427]. https://doi.org/10.1109/JSSC.2008.917427