A 1.5-to-5.0GHz Input-Matched +2dBm P1dB All-Passive Switched-Capacitor Beamforming Receiver Front-End in 65nm CMOS

M.C.M. Soer; Eric A.M. Klumperink; Bram Nauta; Frank Edward van Vliet

doi:10.1109/ISSCC.2012.6176965

A 1.5-to-5.0GHz Input-Matched +2dBm P1dB All-Passive Switched-Capacitor Beamforming Receiver Front-End in 65nm CMOS

M.C.M. Soer, Eric A.M. Klumperink, Bram Nauta, Frank Edward van Vliet

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

20 Citations (Scopus)

206 Downloads (Pure)

Abstract

Phased arrays in CMOS for consumer communication bands aim to enhance receiver performance by exploiting beamforming with antenna arrays. Sensitivity increases with the number of antenna elements through array gain and interferers can be cancelled through the spatial filtering of the beam pattern [1]. For the latter, the linearity of the receiver before the beamforming summing point becomes a bottleneck as interferers are not cancelled yet. Phase shifting in the LO domain reduces the complexity in the signal path and enables the use of linear signal blocks, but has high requirements on the multiphase LO generation [2]. On the other hand, a switched-capacitor phase shifter can be very linear, but is limited by the linearity of the necessary input matching and element summing gm-stages [3]. This paper proposes a fully passive phased-array receiver front-end which implements impedance matching, phase shifting and element summing with only switched-capacitor stages for a high linearity.

Original language	English
Title of host publication	2012 IEEE International Solid-State Circuits Conference
Place of Publication	Piscataway
Publisher	IEEE
Pages	174-176
Number of pages	3
ISBN (Print)	978-1-4673-0376-7
DOIs	https://doi.org/10.1109/ISSCC.2012.6176965
Publication status	Published - 19 Feb 2012
Event	IEEE International Solid-State Circuits Conference, ISSCC 2012 - San Francisco, United States Duration: 19 Feb 2012 → 23 Feb 2012

Conference

Conference	IEEE International Solid-State Circuits Conference, ISSCC 2012
Abbreviated title	ISSCC
Country/Territory	United States
City	San Francisco
Period	19/02/12 → 23/02/12

Keywords

IR-80242
EWI-21784
METIS-286336

Access to Document

10.1109/ISSCC.2012.6176965

Soer_ISSCC_2012Accepted author version, 1.52 MB

Cite this

@inproceedings{33a83e653b31465b95de0881acf4f2d9,

title = "A 1.5-to-5.0GHz Input-Matched +2dBm P1dB All-Passive Switched-Capacitor Beamforming Receiver Front-End in 65nm CMOS",

abstract = "Phased arrays in CMOS for consumer communication bands aim to enhance receiver performance by exploiting beamforming with antenna arrays. Sensitivity increases with the number of antenna elements through array gain and interferers can be cancelled through the spatial filtering of the beam pattern [1]. For the latter, the linearity of the receiver before the beamforming summing point becomes a bottleneck as interferers are not cancelled yet. Phase shifting in the LO domain reduces the complexity in the signal path and enables the use of linear signal blocks, but has high requirements on the multiphase LO generation [2]. On the other hand, a switched-capacitor phase shifter can be very linear, but is limited by the linearity of the necessary input matching and element summing gm-stages [3]. This paper proposes a fully passive phased-array receiver front-end which implements impedance matching, phase shifting and element summing with only switched-capacitor stages for a high linearity.",

keywords = "IR-80242, EWI-21784, METIS-286336",

author = "M.C.M. Soer and Klumperink, {Eric A.M.} and Bram Nauta and {van Vliet}, {Frank Edward}",

year = "2012",

month = feb,

day = "19",

doi = "10.1109/ISSCC.2012.6176965",

language = "English",

isbn = "978-1-4673-0376-7",

pages = "174--176",

booktitle = "2012 IEEE International Solid-State Circuits Conference",

publisher = "IEEE",

address = "United States",

note = "IEEE International Solid-State Circuits Conference, ISSCC 2012, ISSCC ; Conference date: 19-02-2012 Through 23-02-2012",

}

Soer, MCM, Klumperink, EAM , Nauta, B & van Vliet, FE 2012, A 1.5-to-5.0GHz Input-Matched +2dBm P1dB All-Passive Switched-Capacitor Beamforming Receiver Front-End in 65nm CMOS. in 2012 IEEE International Solid-State Circuits Conference. IEEE, Piscataway, pp. 174-176, IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, California, United States, 19/02/12. https://doi.org/10.1109/ISSCC.2012.6176965

A 1.5-to-5.0GHz Input-Matched +2dBm P1dB All-Passive Switched-Capacitor Beamforming Receiver Front-End in 65nm CMOS. / Soer, M.C.M.; Klumperink, Eric A.M.; Nauta, Bram et al.
2012 IEEE International Solid-State Circuits Conference. Piscataway: IEEE, 2012. p. 174-176.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A 1.5-to-5.0GHz Input-Matched +2dBm P1dB All-Passive Switched-Capacitor Beamforming Receiver Front-End in 65nm CMOS

AU - Soer, M.C.M.

AU - Klumperink, Eric A.M.

AU - Nauta, Bram

AU - van Vliet, Frank Edward

PY - 2012/2/19

Y1 - 2012/2/19

N2 - Phased arrays in CMOS for consumer communication bands aim to enhance receiver performance by exploiting beamforming with antenna arrays. Sensitivity increases with the number of antenna elements through array gain and interferers can be cancelled through the spatial filtering of the beam pattern [1]. For the latter, the linearity of the receiver before the beamforming summing point becomes a bottleneck as interferers are not cancelled yet. Phase shifting in the LO domain reduces the complexity in the signal path and enables the use of linear signal blocks, but has high requirements on the multiphase LO generation [2]. On the other hand, a switched-capacitor phase shifter can be very linear, but is limited by the linearity of the necessary input matching and element summing gm-stages [3]. This paper proposes a fully passive phased-array receiver front-end which implements impedance matching, phase shifting and element summing with only switched-capacitor stages for a high linearity.

AB - Phased arrays in CMOS for consumer communication bands aim to enhance receiver performance by exploiting beamforming with antenna arrays. Sensitivity increases with the number of antenna elements through array gain and interferers can be cancelled through the spatial filtering of the beam pattern [1]. For the latter, the linearity of the receiver before the beamforming summing point becomes a bottleneck as interferers are not cancelled yet. Phase shifting in the LO domain reduces the complexity in the signal path and enables the use of linear signal blocks, but has high requirements on the multiphase LO generation [2]. On the other hand, a switched-capacitor phase shifter can be very linear, but is limited by the linearity of the necessary input matching and element summing gm-stages [3]. This paper proposes a fully passive phased-array receiver front-end which implements impedance matching, phase shifting and element summing with only switched-capacitor stages for a high linearity.

KW - IR-80242

KW - EWI-21784

KW - METIS-286336

U2 - 10.1109/ISSCC.2012.6176965

DO - 10.1109/ISSCC.2012.6176965

M3 - Conference contribution

SN - 978-1-4673-0376-7

SP - 174

EP - 176

BT - 2012 IEEE International Solid-State Circuits Conference

PB - IEEE

CY - Piscataway

T2 - IEEE International Solid-State Circuits Conference, ISSCC 2012

Y2 - 19 February 2012 through 23 February 2012

ER -

A 1.5-to-5.0GHz Input-Matched +2dBm P1dB All-Passive Switched-Capacitor Beamforming Receiver Front-End in 65nm CMOS

Abstract

Conference

Keywords

Access to Document

Fingerprint

Cite this