A 1.5-to-5.0GHz Input-Matched +2dBm P1dB All-Passive Switched-Capacitor Beamforming Receiver Front-End in 65nm CMOS

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    Abstract

    Phased arrays in CMOS for consumer communication bands aim to enhance receiver performance by exploiting beamforming with antenna arrays. Sensitivity increases with the number of antenna elements through array gain and interferers can be cancelled through the spatial filtering of the beam pattern [1]. For the latter, the linearity of the receiver before the beamforming summing point becomes a bottleneck as interferers are not cancelled yet. Phase shifting in the LO domain reduces the complexity in the signal path and enables the use of linear signal blocks, but has high requirements on the multiphase LO generation [2]. On the other hand, a switched-capacitor phase shifter can be very linear, but is limited by the linearity of the necessary input matching and element summing gm-stages [3]. This paper proposes a fully passive phased-array receiver front-end which implements impedance matching, phase shifting and element summing with only switched-capacitor stages for a high linearity.
    Original languageEnglish
    Title of host publication2012 IEEE International Solid-State Circuits Conference
    Place of PublicationPiscataway
    PublisherIEEE
    Pages174-176
    Number of pages3
    ISBN (Print)978-1-4673-0376-7
    DOIs
    Publication statusPublished - 19 Feb 2012
    EventIEEE International Solid-State Circuits Conference, ISSCC 2012 - San Francisco, United States
    Duration: 19 Feb 201223 Feb 2012

    Conference

    ConferenceIEEE International Solid-State Circuits Conference, ISSCC 2012
    Abbreviated titleISSCC
    CountryUnited States
    CitySan Francisco
    Period19/02/1223/02/12

    Keywords

    • IR-80242
    • EWI-21784
    • METIS-286336

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