A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS

S.M. Louwsma, Adrianus Johannes Maria van Tuijl, Maarten Vertregt, Peter C.S. Scholtens, Bram Nauta

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    Abstract

    A 1.6 GS/s track and hold circuit that produces 16 interleaving, 100 MS/s voltage buffered output signals is presented. The achieved SFDR for a 950 MHz full scale input signal is 50 dB. Phase alignment is better than 2 ps and aperture uncertainty is less than 0.8 ps (RMS). The chip includes two analog to digital converters and a switching matrix to accommodate measurement of all sampled output signals and their timing relation. Chip area is 0.14 mm2, excluding the AD converters. The chip is made in a 0.12 μm, 1.2 V CMOS process. Power consumption of the interleaving T/H circuit is 32 mW.
    Original languageEnglish
    Title of host publicationthe 30th European Solid-State Circuits Conference, 2004 (ESSCIRC 2004)
    Place of PublicationLeuven
    PublisherIEEE
    Pages343-346
    Number of pages4
    ISBN (Print)0780384806
    DOIs
    Publication statusPublished - Sep 2004
    Event30th European Solid-State Circuits Conference, ESSCIRC 2004 - Leuven, Belgium
    Duration: 21 Sep 200423 Sep 2004
    Conference number: 30

    Publication series

    Name
    PublisherIEEE

    Conference

    Conference30th European Solid-State Circuits Conference, ESSCIRC 2004
    Abbreviated titleESSCIRC
    CountryBelgium
    CityLeuven
    Period21/09/0423/09/04

    Keywords

    • EWI-14492
    • METIS-219762
    • IR-48365

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