A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS

S.M. Louwsma; Adrianus Johannes Maria van Tuijl; Maarten Vertregt; Peter C.S. Scholtens; Bram Nauta

doi:10.1109/ESSCIR.2004.1356688

A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS

S.M. Louwsma, Adrianus Johannes Maria van Tuijl, Maarten Vertregt, Peter C.S. Scholtens, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

16 Citations (Scopus)

125 Downloads (Pure)

Abstract

A 1.6 GS/s track and hold circuit that produces 16 interleaving, 100 MS/s voltage buffered output signals is presented. The achieved SFDR for a 950 MHz full scale input signal is 50 dB. Phase alignment is better than 2 ps and aperture uncertainty is less than 0.8 ps (RMS). The chip includes two analog to digital converters and a switching matrix to accommodate measurement of all sampled output signals and their timing relation. Chip area is 0.14 mm2, excluding the AD converters. The chip is made in a 0.12 μm, 1.2 V CMOS process. Power consumption of the interleaving T/H circuit is 32 mW.

Original language	English
Title of host publication	the 30th European Solid-State Circuits Conference, 2004 (ESSCIRC 2004)
Place of Publication	Leuven
Publisher	IEEE
Pages	343-346
Number of pages	4
ISBN (Print)	0780384806
DOIs	https://doi.org/10.1109/ESSCIR.2004.1356688
Publication status	Published - Sept 2004
Event	30th European Solid-State Circuits Conference, ESSCIRC 2004 - Leuven, Belgium Duration: 21 Sept 2004 → 23 Sept 2004 Conference number: 30

Publication series

Name
Publisher	IEEE

Conference

Conference	30th European Solid-State Circuits Conference, ESSCIRC 2004
Abbreviated title	ESSCIRC
Country/Territory	Belgium
City	Leuven
Period	21/09/04 → 23/09/04

Keywords

EWI-14492
METIS-219762
IR-48365

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10.1109/ESSCIR.2004.1356688

01356688Final published version, 320 KB

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@inproceedings{b39990087d3942e1b75b79f7c669415a,

title = "A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS",

abstract = "A 1.6 GS/s track and hold circuit that produces 16 interleaving, 100 MS/s voltage buffered output signals is presented. The achieved SFDR for a 950 MHz full scale input signal is 50 dB. Phase alignment is better than 2 ps and aperture uncertainty is less than 0.8 ps (RMS). The chip includes two analog to digital converters and a switching matrix to accommodate measurement of all sampled output signals and their timing relation. Chip area is 0.14 mm2, excluding the AD converters. The chip is made in a 0.12 μm, 1.2 V CMOS process. Power consumption of the interleaving T/H circuit is 32 mW.",

keywords = "EWI-14492, METIS-219762, IR-48365",

author = "S.M. Louwsma and {van Tuijl}, {Adrianus Johannes Maria} and Maarten Vertregt and Scholtens, {Peter C.S.} and Bram Nauta",

year = "2004",

month = sep,

doi = "10.1109/ESSCIR.2004.1356688",

language = "English",

isbn = "0780384806",

publisher = "IEEE",

pages = "343--346",

booktitle = "the 30th European Solid-State Circuits Conference, 2004 (ESSCIRC 2004)",

address = "United States",

note = "30th European Solid-State Circuits Conference, ESSCIRC 2004, ESSCIRC ; Conference date: 21-09-2004 Through 23-09-2004",

}

Louwsma, SM, van Tuijl, AJM, Vertregt, M, Scholtens, PCS & Nauta, B 2004, A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS. in the 30th European Solid-State Circuits Conference, 2004 (ESSCIRC 2004). IEEE, Leuven, pp. 343-346, 30th European Solid-State Circuits Conference, ESSCIRC 2004, Leuven, Belgium, 21/09/04. https://doi.org/10.1109/ESSCIR.2004.1356688

A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS. / Louwsma, S.M.; van Tuijl, Adrianus Johannes Maria; Vertregt, Maarten et al.
the 30th European Solid-State Circuits Conference, 2004 (ESSCIRC 2004). Leuven: IEEE, 2004. p. 343-346.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - Louwsma, S.M.

AU - van Tuijl, Adrianus Johannes Maria

AU - Vertregt, Maarten

AU - Scholtens, Peter C.S.

AU - Nauta, Bram

N1 - Conference code: 30

PY - 2004/9

Y1 - 2004/9

N2 - A 1.6 GS/s track and hold circuit that produces 16 interleaving, 100 MS/s voltage buffered output signals is presented. The achieved SFDR for a 950 MHz full scale input signal is 50 dB. Phase alignment is better than 2 ps and aperture uncertainty is less than 0.8 ps (RMS). The chip includes two analog to digital converters and a switching matrix to accommodate measurement of all sampled output signals and their timing relation. Chip area is 0.14 mm2, excluding the AD converters. The chip is made in a 0.12 μm, 1.2 V CMOS process. Power consumption of the interleaving T/H circuit is 32 mW.

AB - A 1.6 GS/s track and hold circuit that produces 16 interleaving, 100 MS/s voltage buffered output signals is presented. The achieved SFDR for a 950 MHz full scale input signal is 50 dB. Phase alignment is better than 2 ps and aperture uncertainty is less than 0.8 ps (RMS). The chip includes two analog to digital converters and a switching matrix to accommodate measurement of all sampled output signals and their timing relation. Chip area is 0.14 mm2, excluding the AD converters. The chip is made in a 0.12 μm, 1.2 V CMOS process. Power consumption of the interleaving T/H circuit is 32 mW.

KW - EWI-14492

KW - METIS-219762

KW - IR-48365

U2 - 10.1109/ESSCIR.2004.1356688

DO - 10.1109/ESSCIR.2004.1356688

M3 - Conference contribution

SN - 0780384806

SP - 343

EP - 346

BT - the 30th European Solid-State Circuits Conference, 2004 (ESSCIRC 2004)

PB - IEEE

CY - Leuven

T2 - 30th European Solid-State Circuits Conference, ESSCIRC 2004

Y2 - 21 September 2004 through 23 September 2004

ER -

A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS

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