@inproceedings{abf81b4136d2455cb2a767dbbe03c60e,
title = "A 1.9 μW 4.4 fJ/conversion-step, 10 bit, 1 MS/s charge redistribution ADC",
abstract = "A 10b SAR ADC uses a charge redistribution DAC, a two-stage comparator, and a delay-line-based controller. The ADC does not use any static bias current and power consumption is proportional to sample rate. At 1MS/s, the ADC uses 1.9μW. With 8.75 ENOB, the resulting FOM is 4.4fJ/conversion-step.",
keywords = "2023 OA procedure",
author = "{van Elzakker}, Michiel and {van Tuijl}, Ed and Paul Geraedts and Daniel Schinkel and Eric Klumperink and Bram Nauta",
year = "2008",
month = feb,
day = "5",
doi = "10.1109/ISSCC.2008.4523148",
language = "English",
isbn = "978-1-4244-2010-0",
series = "IEEE International Solid-State Circuits Conference - Digest of Technical Papers",
publisher = "IEEE",
pages = "244--245+610",
booktitle = "Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC)",
address = "United States",
note = "IEEE International Solid- State Circuits Conference, ISSCC 2008, ISSCC ; Conference date: 03-02-2008 Through 07-02-2008",
}