A 1.9 μW 4.4 fJ/conversion-step, 10 bit, 1 MS/s charge redistribution ADC

Michel van Elzakker, Adrianus Johannes Maria van Tuijl, P.F.J. Geraedts, Daniel Schinkel, Eric A.M. Klumperink, Bram Nauta

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    219 Citations (Scopus)
    97 Downloads (Pure)

    Abstract

    A 10b SAR ADC uses a charge redistribution DAC, a two-stage comparator, and a delay-line-based controller. The ADC does not use any static bias current and power consumption is proportional to sample rate. At 1MS/s, the ADC uses 1.9μW. With 8.75 ENOB, the resulting FOM is 4.4fJ/conversion-step.
    Original languageEnglish
    Title of host publicationProceedings of the IEEE International Solid-State Circuits Conference (ISSCC)
    Place of PublicationPiscataway
    PublisherIEEE
    Pages244-245+610
    ISBN (Print)978-1-4244-2010-0
    DOIs
    Publication statusPublished - 5 Feb 2008
    EventIEEE International Solid- State Circuits Conference, ISSCC 2008 - San Francisco, United States
    Duration: 3 Feb 20087 Feb 2008

    Conference

    ConferenceIEEE International Solid- State Circuits Conference, ISSCC 2008
    Abbreviated titleISSCC
    CountryUnited States
    CitySan Francisco
    Period3/02/087/02/08

    Keywords

    • EWI-13054
    • METIS-251074
    • IR-64872

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