A 1.9 μW 4.4 fJ/conversion-step, 10 bit, 1 MS/s charge redistribution ADC

Michel van Elzakker; Adrianus Johannes Maria van Tuijl; P.F.J. Geraedts; Daniel Schinkel; Eric A.M. Klumperink; Bram Nauta

doi:10.1109/ISSCC.2008.4523148

A 1.9 μW 4.4 fJ/conversion-step, 10 bit, 1 MS/s charge redistribution ADC

Michel van Elzakker, Adrianus Johannes Maria van Tuijl, P.F.J. Geraedts, Daniel Schinkel, Eric A.M. Klumperink, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

241 Citations (Scopus)

243 Downloads (Pure)

Abstract

A 10b SAR ADC uses a charge redistribution DAC, a two-stage comparator, and a delay-line-based controller. The ADC does not use any static bias current and power consumption is proportional to sample rate. At 1MS/s, the ADC uses 1.9μW. With 8.75 ENOB, the resulting FOM is 4.4fJ/conversion-step.

Original language	English
Title of host publication	Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC)
Place of Publication	Piscataway
Publisher	IEEE
Pages	244-245+610
ISBN (Print)	978-1-4244-2010-0
DOIs	https://doi.org/10.1109/ISSCC.2008.4523148
Publication status	Published - 5 Feb 2008
Event	IEEE International Solid- State Circuits Conference, ISSCC 2008 - San Francisco, United States Duration: 3 Feb 2008 → 7 Feb 2008

Conference

Conference	IEEE International Solid- State Circuits Conference, ISSCC 2008
Abbreviated title	ISSCC
Country/Territory	United States
City	San Francisco
Period	3/02/08 → 7/02/08

Keywords

EWI-13054
METIS-251074
IR-64872

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10.1109/ISSCC.2008.4523148

M._van_Elzakker_IEEE_ISSCC_2008Final published version, 610 KB

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title = "A 1.9 μW 4.4 fJ/conversion-step, 10 bit, 1 MS/s charge redistribution ADC",

abstract = "A 10b SAR ADC uses a charge redistribution DAC, a two-stage comparator, and a delay-line-based controller. The ADC does not use any static bias current and power consumption is proportional to sample rate. At 1MS/s, the ADC uses 1.9μW. With 8.75 ENOB, the resulting FOM is 4.4fJ/conversion-step.",

keywords = "EWI-13054, METIS-251074, IR-64872",

author = "{van Elzakker}, Michel and {van Tuijl}, {Adrianus Johannes Maria} and P.F.J. Geraedts and Daniel Schinkel and Klumperink, {Eric A.M.} and Bram Nauta",

year = "2008",

month = feb,

day = "5",

doi = "10.1109/ISSCC.2008.4523148",

language = "English",

isbn = "978-1-4244-2010-0",

pages = "244--245+610",

booktitle = "Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC)",

publisher = "IEEE",

note = "IEEE International Solid- State Circuits Conference, ISSCC 2008, ISSCC ; Conference date: 03-02-2008 Through 07-02-2008",

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van Elzakker, M, van Tuijl, AJM, Geraedts, PFJ, Schinkel, D, Klumperink, EAM & Nauta, B 2008, A 1.9 μW 4.4 fJ/conversion-step, 10 bit, 1 MS/s charge redistribution ADC. in Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC). IEEE, Piscataway, pp. 244-245+610, IEEE International Solid- State Circuits Conference, ISSCC 2008, San Francisco, California, United States, 3/02/08. https://doi.org/10.1109/ISSCC.2008.4523148

A 1.9 μW 4.4 fJ/conversion-step, 10 bit, 1 MS/s charge redistribution ADC. / van Elzakker, Michel; van Tuijl, Adrianus Johannes Maria; Geraedts, P.F.J. et al.

Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC). Piscataway : IEEE, 2008. p. 244-245+610.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A 1.9 μW 4.4 fJ/conversion-step, 10 bit, 1 MS/s charge redistribution ADC

AU - van Elzakker, Michel

AU - van Tuijl, Adrianus Johannes Maria

AU - Geraedts, P.F.J.

AU - Schinkel, Daniel

AU - Klumperink, Eric A.M.

AU - Nauta, Bram

PY - 2008/2/5

Y1 - 2008/2/5

N2 - A 10b SAR ADC uses a charge redistribution DAC, a two-stage comparator, and a delay-line-based controller. The ADC does not use any static bias current and power consumption is proportional to sample rate. At 1MS/s, the ADC uses 1.9μW. With 8.75 ENOB, the resulting FOM is 4.4fJ/conversion-step.

AB - A 10b SAR ADC uses a charge redistribution DAC, a two-stage comparator, and a delay-line-based controller. The ADC does not use any static bias current and power consumption is proportional to sample rate. At 1MS/s, the ADC uses 1.9μW. With 8.75 ENOB, the resulting FOM is 4.4fJ/conversion-step.

KW - EWI-13054

KW - METIS-251074

KW - IR-64872

U2 - 10.1109/ISSCC.2008.4523148

DO - 10.1109/ISSCC.2008.4523148

M3 - Conference contribution

SN - 978-1-4244-2010-0

SP - 244-245+610

BT - Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC)

PB - IEEE

CY - Piscataway

T2 - IEEE International Solid- State Circuits Conference, ISSCC 2008

Y2 - 3 February 2008 through 7 February 2008

ER -

A 1.9 μW 4.4 fJ/conversion-step, 10 bit, 1 MS/s charge redistribution ADC

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Keywords

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