Abstract
A 10b SAR ADC uses a charge redistribution DAC, a two-stage comparator, and a delay-line-based controller. The ADC does not use any static bias current and power consumption is proportional to sample rate. At 1MS/s, the ADC uses 1.9μW. With 8.75 ENOB, the resulting FOM is 4.4fJ/conversion-step.
Original language | English |
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Title of host publication | Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC) |
Place of Publication | Piscataway |
Publisher | IEEE |
Pages | 244-245+610 |
ISBN (Print) | 978-1-4244-2010-0 |
DOIs | |
Publication status | Published - 5 Feb 2008 |
Event | IEEE International Solid- State Circuits Conference, ISSCC 2008 - San Francisco, United States Duration: 3 Feb 2008 → 7 Feb 2008 |
Conference
Conference | IEEE International Solid- State Circuits Conference, ISSCC 2008 |
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Abbreviated title | ISSCC |
Country/Territory | United States |
City | San Francisco |
Period | 3/02/08 → 7/02/08 |
Keywords
- EWI-13054
- METIS-251074
- IR-64872