A 200 µA Duty-Cycled PLL for Wireless Sensor Nodes

S. Drago, Domine Leenaerts, Bram Nauta, Fabio Sebastiano, Kofi Makinwa, Lucien Breems

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    A duty-cycled PLL operating in burst mode is presented. It is an essential building block of a moderately accurate low-power frequency synthesizer suitable for use in nodes for Wireless Sensor Networks. Once in lock, the PLL's frequency error is less than 0.1% (rms). Fabricated in a baseline 65 nm CMOS process, the PLL occupies 0.19X0.15 mm2 and draws 200 µA from a 1.3-V supply when generating a 1 GHz signal with a duty cycle of 10%.
    Original languageEnglish
    Title of host publicationProceedings of the Esscirc2009
    Place of PublicationPiscataway
    Number of pages4
    ISBN (Print)978-1-4244-4353-6
    Publication statusPublished - 14 Sep 2009
    Event35th European Solid-State Circuits Conference, ESSCIRC 2009 - Athene, Greece
    Duration: 14 Sep 200918 Sep 2009
    Conference number: 35


    Conference35th European Solid-State Circuits Conference, ESSCIRC 2009
    Abbreviated titleESSCIRC



    • IR-69822
    • EWI-16091
    • METIS-265229

    Cite this

    Drago, S., Leenaerts, D., Nauta, B., Sebastiano, F., Makinwa, K., & Breems, L. (2009). A 200 µA Duty-Cycled PLL for Wireless Sensor Nodes. In Proceedings of the Esscirc2009 (pp. 132-135). Piscataway: IEEE. https://doi.org/10.1109/ESSCIRC.2009.5325979