A 200 µA Duty-Cycled PLL for Wireless Sensor Nodes in 65nm CMOS

S. Drago, Dominicus M.W. Leenaerts, Bram Nauta, Fabio Sebastiano, Kofi A.A. Makinwa, Lucien J. Breems

    Research output: Contribution to journalArticleAcademicpeer-review

    24 Citations (Scopus)
    64 Downloads (Pure)

    Abstract

    Abstract The design of a duty-cycled PLL (DCPLL) capable of burst mode operation is presented. The proposed DCPLL is a moderately accurate low-power high-frequency synthesizer suitable for use in nodes for wireless sensor networks (WSN). Thanks to a dual loop configuration, the PLL's total frequency error, once in lock, is less than 0.25% from 300 MHz to 1.2 GHz. It employs a fast start-up DCO which enables its operation at duty-cycles as low as 10%. Fabricated in a baseline 65 nm CMOS technology, the DCPLL circuit occupies 0.19 x 0.15 mm2 and draws 200 μA from a 1.3 V supply when generating bursts of 1 GHz signal with a 10% duty-cycle.
    Original languageEnglish
    Pages (from-to)1305-1315
    Number of pages11
    JournalIEEE journal of solid-state circuits
    Volume45
    Issue number7
    DOIs
    Publication statusPublished - 1 Jul 2010

    Keywords

    • METIS-271067
    • IR-73660
    • CMOS
    • Duty-Cycle
    • Wireless Sensor Networks
    • WSN
    • PLL
    • frequency stability
    • frequency synthesizer
    • fully integrated
    • ultra-low power
    • EWI-18584

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