A 200 µA Duty-Cycled PLL for Wireless Sensor Nodes

S. Drago; Domine Leenaerts; Bram Nauta; Fabio Sebastiano; Kofi Makinwa; Lucien Breems

doi:10.1109/ESSCIRC.2009.5325979

A 200 µA Duty-Cycled PLL for Wireless Sensor Nodes

S. Drago
, Domine Leenaerts
, Bram Nauta
, Fabio Sebastiano
, Kofi Makinwa
, Lucien Breems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

2 Citations (Scopus)

221 Downloads (Pure)

Abstract

A duty-cycled PLL operating in burst mode is presented. It is an essential building block of a moderately accurate low-power frequency synthesizer suitable for use in nodes for Wireless Sensor Networks. Once in lock, the PLL's frequency error is less than 0.1% (rms). Fabricated in a baseline 65 nm CMOS process, the PLL occupies 0.19X0.15 mm2 and draws 200 µA from a 1.3-V supply when generating a 1 GHz signal with a duty cycle of 10%.

Original language	English
Title of host publication	Proceedings of the Esscirc2009
Place of Publication	Piscataway
Publisher	IEEE
Pages	132-135
Number of pages	4
ISBN (Print)	978-1-4244-4353-6
DOIs	https://doi.org/10.1109/ESSCIRC.2009.5325979
Publication status	Published - 14 Sept 2009
Event	35th European Solid-State Circuits Conference, ESSCIRC 2009 - Athene, Greece Duration: 14 Sept 2009 → 18 Sept 2009 Conference number: 35

Conference

Conference	35th European Solid-State Circuits Conference, ESSCIRC 2009
Abbreviated title	ESSCIRC
Country/Territory	Greece
City	Athene
Period	14/09/09 → 18/09/09

Keywords

IR-69822
EWI-16091
METIS-265229

Access to Document

10.1109/ESSCIRC.2009.5325979

Drago_S._ESSCIRC2009Accepted author version, 236 KB

Cite this

@inproceedings{86601ef2e397437fb50a8748c188e043,

title = "A 200 µA Duty-Cycled PLL for Wireless Sensor Nodes",

abstract = "A duty-cycled PLL operating in burst mode is presented. It is an essential building block of a moderately accurate low-power frequency synthesizer suitable for use in nodes for Wireless Sensor Networks. Once in lock, the PLL's frequency error is less than 0.1\% (rms). Fabricated in a baseline 65 nm CMOS process, the PLL occupies 0.19X0.15 mm2 and draws 200 µA from a 1.3-V supply when generating a 1 GHz signal with a duty cycle of 10\%.",

keywords = "IR-69822, EWI-16091, METIS-265229",

author = "S. Drago and Domine Leenaerts and Bram Nauta and Fabio Sebastiano and Kofi Makinwa and Lucien Breems",

year = "2009",

month = sep,

day = "14",

doi = "10.1109/ESSCIRC.2009.5325979",

language = "English",

isbn = "978-1-4244-4353-6",

pages = "132--135",

booktitle = "Proceedings of the Esscirc2009",

publisher = "IEEE",

address = "United States",

note = "35th European Solid-State Circuits Conference, ESSCIRC 2009, ESSCIRC ; Conference date: 14-09-2009 Through 18-09-2009",

}

TY - GEN

T1 - A 200 µA Duty-Cycled PLL for Wireless Sensor Nodes

AU - Drago, S.

AU - Leenaerts, Domine

AU - Nauta, Bram

AU - Sebastiano, Fabio

AU - Makinwa, Kofi

AU - Breems, Lucien

N1 - Conference code: 35

PY - 2009/9/14

Y1 - 2009/9/14

N2 - A duty-cycled PLL operating in burst mode is presented. It is an essential building block of a moderately accurate low-power frequency synthesizer suitable for use in nodes for Wireless Sensor Networks. Once in lock, the PLL's frequency error is less than 0.1% (rms). Fabricated in a baseline 65 nm CMOS process, the PLL occupies 0.19X0.15 mm2 and draws 200 µA from a 1.3-V supply when generating a 1 GHz signal with a duty cycle of 10%.

AB - A duty-cycled PLL operating in burst mode is presented. It is an essential building block of a moderately accurate low-power frequency synthesizer suitable for use in nodes for Wireless Sensor Networks. Once in lock, the PLL's frequency error is less than 0.1% (rms). Fabricated in a baseline 65 nm CMOS process, the PLL occupies 0.19X0.15 mm2 and draws 200 µA from a 1.3-V supply when generating a 1 GHz signal with a duty cycle of 10%.

KW - IR-69822

KW - EWI-16091

KW - METIS-265229

U2 - 10.1109/ESSCIRC.2009.5325979

DO - 10.1109/ESSCIRC.2009.5325979

M3 - Conference contribution

SN - 978-1-4244-4353-6

SP - 132

EP - 135

BT - Proceedings of the Esscirc2009

PB - IEEE

CY - Piscataway

T2 - 35th European Solid-State Circuits Conference, ESSCIRC 2009

Y2 - 14 September 2009 through 18 September 2009

ER -

A 200 µA Duty-Cycled PLL for Wireless Sensor Nodes

Abstract

Conference

Keywords

Access to Document

Fingerprint

Cite this