A 20dBm outphasing class E PA with high efficiency at power back-off in 65nm CMOS technology

Ali  Ghahremani; Anne J. Annema; Bram  Nauta

doi:10.1109/RFIC.2017.7969087

A 20dBm outphasing class E PA with high efficiency at power back-off in 65nm CMOS technology

Ali Ghahremani, Anne J. Annema, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

5 Citations (Scopus)

268 Downloads (Pure)

Abstract

This paper presents an outphasing class E PA (OEPA) in a 65nm CMOS technology, using a pcb transmission-line based power combiner. The OEPA can provide +20dBm output power from VDD=1.25V at 1.4GHz with 61% drain efficiency (DE) and 58% power added efficiency (PAE). We introduced a technique to rotate and shift power and efficiency contours of the two branch PAs that enables more than 44dB output power dynamic range, reduces switch voltage stresses compared to conventional OEPAs and enables 41% DE and 24% PAE at 12.5dB back-off.

Original language	English
Title of host publication	2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
Place of Publication	Piscataway
Publisher	IEEE
Pages	340-343
Number of pages	4
ISBN (Electronic)	978-1-5090-4626-3
ISBN (Print)	978-1-5090-4627-0
DOIs	https://doi.org/10.1109/RFIC.2017.7969087
Publication status	Published - 6 Jun 2017
Event	2017 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2017 - Hawaii Convention Center, Honolulu, United States Duration: 4 Jun 2017 → 6 Jun 2017 http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7961542

Conference

Conference	2017 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2017
Abbreviated title	RFIC
Country	United States
City	Honolulu
Period	4/06/17 → 6/06/17
Internet address	http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7961542

Access to Document

10.1109/RFIC.2017.7969087

RFIC_ 2017_ALI_GhahremaniAccepted author version, 609 KB

Cite this

@inproceedings{98156cd9ff254a5d89206f16559e79cc,

title = "A 20dBm outphasing class E PA with high efficiency at power back-off in 65nm CMOS technology",

abstract = "This paper presents an outphasing class E PA (OEPA) in a 65nm CMOS technology, using a pcb transmission-line based power combiner. The OEPA can provide +20dBm output power from VDD=1.25V at 1.4GHz with 61% drain efficiency (DE) and 58% power added efficiency (PAE). We introduced a technique to rotate and shift power and efficiency contours of the two branch PAs that enables more than 44dB output power dynamic range, reduces switch voltage stresses compared to conventional OEPAs and enables 41% DE and 24% PAE at 12.5dB back-off.",

author = "Ali Ghahremani and Annema, {Anne J.} and Bram Nauta",

year = "2017",

month = jun,

day = "6",

doi = "10.1109/RFIC.2017.7969087",

language = "English",

isbn = "978-1-5090-4627-0",

pages = "340--343",

booktitle = "2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)",

publisher = "IEEE",

address = "United States",

note = "2017 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2017, RFIC ; Conference date: 04-06-2017 Through 06-06-2017",

url = "http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7961542",

}

Ghahremani, A, Annema, AJ & Nauta, B 2017, A 20dBm outphasing class E PA with high efficiency at power back-off in 65nm CMOS technology. in 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). IEEE, Piscataway, pp. 340-343, 2017 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2017, Honolulu, United States, 4/06/17. https://doi.org/10.1109/RFIC.2017.7969087

TY - GEN

T1 - A 20dBm outphasing class E PA with high efficiency at power back-off in 65nm CMOS technology

AU - Ghahremani, Ali

AU - Annema, Anne J.

AU - Nauta, Bram

PY - 2017/6/6

Y1 - 2017/6/6

N2 - This paper presents an outphasing class E PA (OEPA) in a 65nm CMOS technology, using a pcb transmission-line based power combiner. The OEPA can provide +20dBm output power from VDD=1.25V at 1.4GHz with 61% drain efficiency (DE) and 58% power added efficiency (PAE). We introduced a technique to rotate and shift power and efficiency contours of the two branch PAs that enables more than 44dB output power dynamic range, reduces switch voltage stresses compared to conventional OEPAs and enables 41% DE and 24% PAE at 12.5dB back-off.

AB - This paper presents an outphasing class E PA (OEPA) in a 65nm CMOS technology, using a pcb transmission-line based power combiner. The OEPA can provide +20dBm output power from VDD=1.25V at 1.4GHz with 61% drain efficiency (DE) and 58% power added efficiency (PAE). We introduced a technique to rotate and shift power and efficiency contours of the two branch PAs that enables more than 44dB output power dynamic range, reduces switch voltage stresses compared to conventional OEPAs and enables 41% DE and 24% PAE at 12.5dB back-off.

U2 - 10.1109/RFIC.2017.7969087

DO - 10.1109/RFIC.2017.7969087

M3 - Conference contribution

SN - 978-1-5090-4627-0

SP - 340

EP - 343

BT - 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

PB - IEEE

CY - Piscataway

T2 - 2017 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2017

Y2 - 4 June 2017 through 6 June 2017

ER -

A 20dBm outphasing class E PA with high efficiency at power back-off in 65nm CMOS technology

Abstract

Conference

Access to Document

Fingerprint

Cite this