A 20dBm outphasing class E PA with high efficiency at power back-off in 65nm CMOS technology

Ali Ghahremani, Anne J. Annema, Bram Nauta

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    5 Citations (Scopus)
    208 Downloads (Pure)

    Abstract

    This paper presents an outphasing class E PA (OEPA) in a 65nm CMOS technology, using a pcb transmission-line based power combiner. The OEPA can provide +20dBm output power from VDD=1.25V at 1.4GHz with 61% drain efficiency (DE) and 58% power added efficiency (PAE). We introduced a technique to rotate and shift power and efficiency contours of the two branch PAs that enables more than 44dB output power dynamic range, reduces switch voltage stresses compared to conventional OEPAs and enables 41% DE and 24% PAE at 12.5dB back-off.
    Original languageEnglish
    Title of host publication2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
    Place of PublicationPiscataway
    PublisherIEEE
    Pages340-343
    Number of pages4
    ISBN (Electronic)978-1-5090-4626-3
    ISBN (Print)978-1-5090-4627-0
    DOIs
    Publication statusPublished - 6 Jun 2017
    Event2017 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2017 - Hawaii Convention Center, Honolulu, United States
    Duration: 4 Jun 20176 Jun 2017
    http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7961542

    Conference

    Conference2017 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2017
    Abbreviated titleRFIC
    CountryUnited States
    CityHonolulu
    Period4/06/176/06/17
    Internet address

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    Cite this

    Ghahremani, A., Annema, A. J., & Nauta, B. (2017). A 20dBm outphasing class E PA with high efficiency at power back-off in 65nm CMOS technology. In 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) (pp. 340-343). Piscataway: IEEE. https://doi.org/10.1109/RFIC.2017.7969087