A 22-nm FDSOI CMOS Low Noise active balun achieving < -44-dBc HD3 up to 1.5-V p-p output swing over 0.01-5.4-GHz for direct RF sampling applications

Anoop Narayan Bhat*, Ronan A.R. van der Zee, Bram Nauta

*Corresponding author for this work

Research output: Contribution to journalArticleAcademicpeer-review

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Abstract

In this article, we propose a CMOS active balun targeting high linearity up to high voltage swing and over wide bandwidth for direct RF sampling applications. All the blocks of this active balun are derived using a common highly linear building block (HLBB). The HLBB is designed using an inverter with strong source degeneration. To increase the linearity of this HLBB further, its nonlinearity mechanisms are analyzed in detail. A bootstrapping technique is included in the HLBB to reduce the dominant nonlinearity. Furthermore, a pre-distortion technique cancels most of the non-linearity of the output driving stages. All the linearization techniques proposed are robust to process, voltage, and temperature (PVT) changes. The measured results of the active balun realized on-chip in a 22-nm FDSOI CMOS shows &lt;-44-dBc third harmonic distortion (HD3) up to 1.5-V <formula> <tex>${_{{p-p}}}$</tex> </formula> output swing over 0.01-5.4 GHz. The measured gain and phase errors of the balun action are less than 0.5 dB and &#x00B1;5&#x00B0;, respectively. The chip is powered from a 5-V supply and dissipates 925 mW.

Original languageEnglish
Number of pages14
JournalIEEE journal of solid-state circuits
Early online date17 Aug 2021
DOIs
Publication statusE-pub ahead of print/First online - 17 Aug 2021

Keywords

  • active balun
  • bootstrapping
  • degeneration
  • direct RF sampling
  • gigahertz analog-to-digital converter (ADC) front end
  • pre-distortion
  • process
  • voltage
  • and temperature (PVT) robust
  • third harmonic distortion (HD3)

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