Abstract
A clock with low phase-noise/jitter is a prerequisite for high-performance ADCs, wireline and optical data links and radio transceivers. This paper presents a 2.2GHz clock-generation PLL. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. The PLL does not need frequency divider in locked state and achieves a low in-band phase noise values at low power.
Original language | English |
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Title of host publication | IEEE International Solid-State Circuits Conference |
Place of Publication | Piscataway |
Publisher | IEEE |
Pages | 392-393 |
Number of pages | 2 |
ISBN (Print) | 978-1-4244-3458-9 |
DOIs | |
Publication status | Published - 10 Feb 2009 |
Event | IEEE International Solid-State Circuits Conference, ISSCC 2009 - San Francisco, United States Duration: 8 Feb 2009 → 12 Feb 2009 |
Conference
Conference | IEEE International Solid-State Circuits Conference, ISSCC 2009 |
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Abbreviated title | ISSCC |
Country/Territory | United States |
City | San Francisco |
Period | 8/02/09 → 12/02/09 |
Keywords
- METIS-263870
- IR-65506
- EWI-15402