A 2.2GHz 7.6mW Sub-Sampling PLL with -126dBc/Hz In-band Phase Noise and 0.15psrms Jitter in 0.18μm CMOS

X. Gao, Eric A.M. Klumperink, M. Bohsali, Bram Nauta

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    63 Citations (Scopus)
    33 Downloads (Pure)

    Abstract

    A clock with low phase-noise/jitter is a prerequisite for high-performance ADCs, wireline and optical data links and radio transceivers. This paper presents a 2.2GHz clock-generation PLL. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. The PLL does not need frequency divider in locked state and achieves a low in-band phase noise values at low power.
    Original languageEnglish
    Title of host publicationIEEE International Solid-State Circuits Conference
    Place of PublicationPiscataway
    PublisherIEEE Computer Society
    Pages392-393
    Number of pages2
    ISBN (Print)978-1-4244-3458-9
    DOIs
    Publication statusPublished - 10 Feb 2009
    EventIEEE International Solid-State Circuits Conference, ISSCC 2009 - San Francisco, United States
    Duration: 8 Feb 200912 Feb 2009

    Conference

    ConferenceIEEE International Solid-State Circuits Conference, ISSCC 2009
    Abbreviated titleISSCC
    CountryUnited States
    CitySan Francisco
    Period8/02/0912/02/09

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    Keywords

    • METIS-263870
    • IR-65506
    • EWI-15402

    Cite this

    Gao, X., Klumperink, E. A. M., Bohsali, M., & Nauta, B. (2009). A 2.2GHz 7.6mW Sub-Sampling PLL with -126dBc/Hz In-band Phase Noise and 0.15psrms Jitter in 0.18μm CMOS. In IEEE International Solid-State Circuits Conference (pp. 392-393). Piscataway: IEEE Computer Society. https://doi.org/10.1109/ISSCC.2009.4977473