A 2.2GHz 7.6mW Sub-Sampling PLL with -126dBc/Hz In-band Phase Noise and 0.15psrms Jitter in 0.18μm CMOS

X. Gao; Eric A.M. Klumperink; M. Bohsali; Bram Nauta

doi:10.1109/ISSCC.2009.4977473

A 2.2GHz 7.6mW Sub-Sampling PLL with -126dBc/Hz In-band Phase Noise and 0.15psrms Jitter in 0.18μm CMOS

X. Gao
, Eric A.M. Klumperink
, M. Bohsali
, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

73 Citations (Scopus)

279 Downloads (Pure)

Abstract

A clock with low phase-noise/jitter is a prerequisite for high-performance ADCs, wireline and optical data links and radio transceivers. This paper presents a 2.2GHz clock-generation PLL. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. The PLL does not need frequency divider in locked state and achieves a low in-band phase noise values at low power.

Original language	English
Title of host publication	IEEE International Solid-State Circuits Conference
Place of Publication	Piscataway
Publisher	IEEE
Pages	392-393
Number of pages	2
ISBN (Print)	978-1-4244-3458-9
DOIs	https://doi.org/10.1109/ISSCC.2009.4977473
Publication status	Published - 10 Feb 2009
Event	IEEE International Solid-State Circuits Conference, ISSCC 2009 - San Francisco, United States Duration: 8 Feb 2009 → 12 Feb 2009

Conference

Conference	IEEE International Solid-State Circuits Conference, ISSCC 2009
Abbreviated title	ISSCC
Country/Territory	United States
City	San Francisco
Period	8/02/09 → 12/02/09

Keywords

METIS-263870
IR-65506
EWI-15402

Access to Document

10.1109/ISSCC.2009.4977473

Gao_IEEE_feb_2009_A_2.2GHz_7.6mW_Sub-SamplingFinal published version, 701 KB

Cite this

@inproceedings{56eff763c27442749fe32cd5437c34fa,

title = "A 2.2GHz 7.6mW Sub-Sampling PLL with -126dBc/Hz In-band Phase Noise and 0.15psrms Jitter in 0.18μm CMOS",

abstract = "A clock with low phase-noise/jitter is a prerequisite for high-performance ADCs, wireline and optical data links and radio transceivers. This paper presents a 2.2GHz clock-generation PLL. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. The PLL does not need frequency divider in locked state and achieves a low in-band phase noise values at low power.",

keywords = "METIS-263870, IR-65506, EWI-15402",

author = "X. Gao and Klumperink, \{Eric A.M.\} and M. Bohsali and Bram Nauta",

year = "2009",

month = feb,

day = "10",

doi = "10.1109/ISSCC.2009.4977473",

language = "English",

isbn = "978-1-4244-3458-9",

pages = "392--393",

booktitle = "IEEE International Solid-State Circuits Conference",

publisher = "IEEE",

address = "United States",

note = "IEEE International Solid-State Circuits Conference, ISSCC 2009, ISSCC ; Conference date: 08-02-2009 Through 12-02-2009",

}

Gao, X, Klumperink, EAM, Bohsali, M & Nauta, B 2009, A 2.2GHz 7.6mW Sub-Sampling PLL with -126dBc/Hz In-band Phase Noise and 0.15psrms Jitter in 0.18μm CMOS. in IEEE International Solid-State Circuits Conference. IEEE, Piscataway, pp. 392-393, IEEE International Solid-State Circuits Conference, ISSCC 2009, San Francisco, California, United States, 8/02/09. https://doi.org/10.1109/ISSCC.2009.4977473

TY - GEN

T1 - A 2.2GHz 7.6mW Sub-Sampling PLL with -126dBc/Hz In-band Phase Noise and 0.15psrms Jitter in 0.18μm CMOS

AU - Gao, X.

AU - Klumperink, Eric A.M.

AU - Bohsali, M.

AU - Nauta, Bram

PY - 2009/2/10

Y1 - 2009/2/10

N2 - A clock with low phase-noise/jitter is a prerequisite for high-performance ADCs, wireline and optical data links and radio transceivers. This paper presents a 2.2GHz clock-generation PLL. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. The PLL does not need frequency divider in locked state and achieves a low in-band phase noise values at low power.

AB - A clock with low phase-noise/jitter is a prerequisite for high-performance ADCs, wireline and optical data links and radio transceivers. This paper presents a 2.2GHz clock-generation PLL. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. The PLL does not need frequency divider in locked state and achieves a low in-band phase noise values at low power.

KW - METIS-263870

KW - IR-65506

KW - EWI-15402

U2 - 10.1109/ISSCC.2009.4977473

DO - 10.1109/ISSCC.2009.4977473

M3 - Conference contribution

SN - 978-1-4244-3458-9

SP - 392

EP - 393

BT - IEEE International Solid-State Circuits Conference

PB - IEEE

CY - Piscataway

T2 - IEEE International Solid-State Circuits Conference, ISSCC 2009

Y2 - 8 February 2009 through 12 February 2009

ER -

A 2.2GHz 7.6mW Sub-Sampling PLL with -126dBc/Hz In-band Phase Noise and 0.15psrms Jitter in 0.18μm CMOS

Abstract

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Keywords

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