A 2.2GHz Sub-Sampling PLL with 0.16psrms Jitter and -125dBc/Hz In-band Phase Noise at 700μW Loop-Components Power

X. Gao, Eric A.M. Klumperink, Gerard Socci, Mounhir Bohsali, Bram Nauta

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    25 Citations (Scopus)
    30 Downloads (Pure)

    Abstract

    A divider-less PLL exploits a phase detector that directly samples the VCO with a reference clock. No VCO sampling buffer is used while dummy samplers keep the VCO spur <;-56dBc. A modified inverter with low short-circuit current acts as a power efficient reference clock buffer. The 2.2 GHz PLL in 0.18 μm CMOS achieves -125dBc/Hz in-band phase noise with only 700 μW loop-components power.
    Original languageEnglish
    Title of host publicationIEEE Symposium on VLSI Circuits, VLSI 2010
    Place of PublicationPiscataway
    PublisherIEEE
    Pages139-140
    Number of pages2
    ISBN (Print)978-1-4244-5454-9
    DOIs
    Publication statusPublished - 16 Jun 2010
    Event2010 IEEE Symposium on VLSI Circuits, VLSIC 2010 - Honolulu, United States
    Duration: 16 Jun 201018 Jun 2010

    Conference

    Conference2010 IEEE Symposium on VLSI Circuits, VLSIC 2010
    Abbreviated titleVLSIC
    CountryUnited States
    CityHonolulu
    Period16/06/1018/06/10

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    Keywords

    • METIS-275888
    • EWI-19471
    • IR-75865

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