Abstract
A divider-less PLL exploits a phase detector that directly samples the VCO with a reference clock. No VCO sampling buffer is used while dummy samplers keep the VCO spur <;-56dBc. A modified inverter with low short-circuit current acts as a power efficient reference clock buffer. The 2.2 GHz PLL in 0.18 μm CMOS achieves -125dBc/Hz in-band phase noise with only 700 μW loop-components power.
Original language | English |
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Title of host publication | IEEE Symposium on VLSI Circuits, VLSI 2010 |
Place of Publication | Piscataway |
Publisher | IEEE |
Pages | 139-140 |
Number of pages | 2 |
ISBN (Print) | 978-1-4244-5454-9 |
DOIs | |
Publication status | Published - 16 Jun 2010 |
Event | 2010 IEEE Symposium on VLSI Circuits, VLSIC 2010 - Honolulu, United States Duration: 16 Jun 2010 → 18 Jun 2010 |
Conference
Conference | 2010 IEEE Symposium on VLSI Circuits, VLSIC 2010 |
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Abbreviated title | VLSIC |
Country/Territory | United States |
City | Honolulu |
Period | 16/06/10 → 18/06/10 |
Keywords
- METIS-275888
- EWI-19471
- IR-75865