A 2.2GHz Sub-Sampling PLL with 0.16psrms Jitter and -125dBc/Hz In-band Phase Noise at 700μW Loop-Components Power

X. Gao; Eric A.M. Klumperink; Gerard Socci; Mounhir Bohsali; Bram Nauta

doi:10.1109/VLSIC.2010.5560323

A 2.2GHz Sub-Sampling PLL with 0.16psrms Jitter and -125dBc/Hz In-band Phase Noise at 700μW Loop-Components Power

X. Gao
, Eric A.M. Klumperink
, Gerard Socci
, Mounhir Bohsali
, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

49 Citations (Scopus)

513 Downloads (Pure)

Abstract

A divider-less PLL exploits a phase detector that directly samples the VCO with a reference clock. No VCO sampling buffer is used while dummy samplers keep the VCO spur <;-56dBc. A modified inverter with low short-circuit current acts as a power efficient reference clock buffer. The 2.2 GHz PLL in 0.18 μm CMOS achieves -125dBc/Hz in-band phase noise with only 700 μW loop-components power.

Original language	English
Title of host publication	IEEE Symposium on VLSI Circuits, VLSI 2010
Place of Publication	Piscataway
Publisher	IEEE
Pages	139-140
Number of pages	2
ISBN (Print)	978-1-4244-5454-9
DOIs	https://doi.org/10.1109/VLSIC.2010.5560323
Publication status	Published - 16 Jun 2010
Event	2010 IEEE Symposium on VLSI Circuits, VLSIC 2010 - Honolulu, United States Duration: 16 Jun 2010 → 18 Jun 2010

Conference

Conference	2010 IEEE Symposium on VLSI Circuits, VLSIC 2010
Abbreviated title	VLSIC
Country/Territory	United States
City	Honolulu
Period	16/06/10 → 18/06/10

Keywords

METIS-275888
EWI-19471
IR-75865

Access to Document

10.1109/VLSIC.2010.5560323

Gao_VLSI_2010Accepted author version, 241 KB

Cite this

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title = "A 2.2GHz Sub-Sampling PLL with 0.16psrms Jitter and -125dBc/Hz In-band Phase Noise at 700μW Loop-Components Power",

abstract = "A divider-less PLL exploits a phase detector that directly samples the VCO with a reference clock. No VCO sampling buffer is used while dummy samplers keep the VCO spur <;-56dBc. A modified inverter with low short-circuit current acts as a power efficient reference clock buffer. The 2.2 GHz PLL in 0.18 μm CMOS achieves -125dBc/Hz in-band phase noise with only 700 μW loop-components power.",

keywords = "METIS-275888, EWI-19471, IR-75865",

author = "X. Gao and Klumperink, \{Eric A.M.\} and Gerard Socci and Mounhir Bohsali and Bram Nauta",

note = "10.1109/VLSIC.2010.5560323 ; 2010 IEEE Symposium on VLSI Circuits, VLSIC 2010, VLSIC ; Conference date: 16-06-2010 Through 18-06-2010",

year = "2010",

month = jun,

day = "16",

doi = "10.1109/VLSIC.2010.5560323",

language = "English",

isbn = "978-1-4244-5454-9",

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booktitle = "IEEE Symposium on VLSI Circuits, VLSI 2010",

publisher = "IEEE",

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Gao, X, Klumperink, EAM, Socci, G, Bohsali, M & Nauta, B 2010, A 2.2GHz Sub-Sampling PLL with 0.16psrms Jitter and -125dBc/Hz In-band Phase Noise at 700μW Loop-Components Power. in IEEE Symposium on VLSI Circuits, VLSI 2010. IEEE, Piscataway, pp. 139-140, 2010 IEEE Symposium on VLSI Circuits, VLSIC 2010, Honolulu, Hawaii, United States, 16/06/10. https://doi.org/10.1109/VLSIC.2010.5560323

TY - GEN

T1 - A 2.2GHz Sub-Sampling PLL with 0.16psrms Jitter and -125dBc/Hz In-band Phase Noise at 700μW Loop-Components Power

AU - Gao, X.

AU - Klumperink, Eric A.M.

AU - Socci, Gerard

AU - Bohsali, Mounhir

AU - Nauta, Bram

N1 - 10.1109/VLSIC.2010.5560323

PY - 2010/6/16

Y1 - 2010/6/16

N2 - A divider-less PLL exploits a phase detector that directly samples the VCO with a reference clock. No VCO sampling buffer is used while dummy samplers keep the VCO spur <;-56dBc. A modified inverter with low short-circuit current acts as a power efficient reference clock buffer. The 2.2 GHz PLL in 0.18 μm CMOS achieves -125dBc/Hz in-band phase noise with only 700 μW loop-components power.

AB - A divider-less PLL exploits a phase detector that directly samples the VCO with a reference clock. No VCO sampling buffer is used while dummy samplers keep the VCO spur <;-56dBc. A modified inverter with low short-circuit current acts as a power efficient reference clock buffer. The 2.2 GHz PLL in 0.18 μm CMOS achieves -125dBc/Hz in-band phase noise with only 700 μW loop-components power.

KW - METIS-275888

KW - EWI-19471

KW - IR-75865

U2 - 10.1109/VLSIC.2010.5560323

DO - 10.1109/VLSIC.2010.5560323

M3 - Conference contribution

SN - 978-1-4244-5454-9

SP - 139

EP - 140

BT - IEEE Symposium on VLSI Circuits, VLSI 2010

PB - IEEE

CY - Piscataway

T2 - 2010 IEEE Symposium on VLSI Circuits, VLSIC 2010

Y2 - 16 June 2010 through 18 June 2010

ER -

A 2.2GHz Sub-Sampling PLL with 0.16psrms Jitter and -125dBc/Hz In-band Phase Noise at 700μW Loop-Components Power

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Keywords

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