A 16-modulo fractional-N sub-sampling phase-locked loop (SSPLL) with a quadrature voltage-controlled oscillator (VCO) interpolating 16 output phases is presented in this paper. Automatic soft switching between the sub-sampling phase control loop and the frequency control loop is proposed to improve loop robustness against perturbations and interferences, achieving more stable loop dynamics for a larger range of phase errors compared with prior art SSPLL designs. A capacitive phase interpolation network is implemented for 16-phase clock generation starting from quadrature phases. The 16 phases are further utilized to achieve fractional-N operation with a sub-sampling phase detector. This passive phase interpolation at the VCO frequency introduces no extra noise or power and avoids in-band phase noise degradation for fractional-N mode. Implemented in a 130-nm CMOS technology, the SSPLL chip achieves a measured in-band phase noise of -120 dBc/Hz and a measured integrated jitter of 158 fs at 2.4 GHz, while consuming 21 mW with 16 output phases. The measured reference spur and fractional spur levels are -72 and -52 dBc, respectively.