A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS

R.C.H. van de Beek, Cicero S. Vaucher, Domine M.W. Leenaerts, Eric A.M. Klumperink, Bram Nauta

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    39 Citations (Scopus)
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    This paper demonstrates a low-jitter clock multiplier unit that generates a 10-GHz output clock from a 2.5-GHz reference clock. An integrated 10-GHz LC oscillator is locked to the input clock, using a simple and fast phase detector circuit that overcomes the speed limitation of a conventional tri-state phase frequency detector due to the lack of an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18-μm CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8-V supply.
    Original languageEnglish
    Pages (from-to)1862-1872
    Number of pages11
    JournalIEEE journal of solid-state circuits
    Issue number11
    Publication statusPublished - Nov 2004


    • CMOS
    • IR-48798
    • METIS-220546
    • phase locked loops (PLL)
    • phase frequency detector (PFD)
    • clock multiplier unit (CMU)
    • clock multiplication
    • voltage-controlled Oscillator (VCO)
    • frequency detector
    • EWI-14464
    • Charge pump
    • low jitter
    • frequency synthesizer
    • frequency multiplication
    • Phase Noise
    • Phase Detector
    • High speed
    • Low noise
    • Clock Generation


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