A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS

R.C.H. van de Beek; Cicero S. Vaucher; Domine M.W. Leenaerts; Eric A.M. Klumperink; Bram Nauta

doi:10.1109/JSSC.2004.835833

A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS

R.C.H. van de Beek, Cicero S. Vaucher, Domine M.W. Leenaerts, Eric A.M. Klumperink, Bram Nauta

Research output: Contribution to journal › Article › Academic › peer-review

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Abstract

This paper demonstrates a low-jitter clock multiplier unit that generates a 10-GHz output clock from a 2.5-GHz reference clock. An integrated 10-GHz LC oscillator is locked to the input clock, using a simple and fast phase detector circuit that overcomes the speed limitation of a conventional tri-state phase frequency detector due to the lack of an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18-μm CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8-V supply.

Original language	English
Pages (from-to)	1862-1872
Number of pages	11
Journal	IEEE journal of solid-state circuits
Volume	39
Issue number	11
DOIs	https://doi.org/10.1109/JSSC.2004.835833
Publication status	Published - Nov 2004

Keywords

CMOS
IR-48798
METIS-220546
phase locked loops (PLL)
phase frequency detector (PFD)
clock multiplier unit (CMU)
clock multiplication
voltage-controlled Oscillator (VCO)
frequency detector
EWI-14464
Charge pump
low jitter
frequency synthesizer
frequency multiplication
Phase Noise
Phase Detector
High speed
Low noise
Clock Generation

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title = "A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS",

abstract = "This paper demonstrates a low-jitter clock multiplier unit that generates a 10-GHz output clock from a 2.5-GHz reference clock. An integrated 10-GHz LC oscillator is locked to the input clock, using a simple and fast phase detector circuit that overcomes the speed limitation of a conventional tri-state phase frequency detector due to the lack of an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18-μm CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8-V supply.",

keywords = "CMOS, IR-48798, METIS-220546, phase locked loops (PLL), phase frequency detector (PFD), clock multiplier unit (CMU), clock multiplication, voltage-controlled Oscillator (VCO), frequency detector, EWI-14464, Charge pump, low jitter, frequency synthesizer, frequency multiplication, Phase Noise, Phase Detector, High speed, Low noise, Clock Generation",

author = "{van de Beek}, R.C.H. and Vaucher, {Cicero S.} and Leenaerts, {Domine M.W.} and Klumperink, {Eric A.M.} and Bram Nauta",

year = "2004",

month = nov,

doi = "10.1109/JSSC.2004.835833",

language = "English",

volume = "39",

pages = "1862--1872",

journal = "IEEE journal of solid-state circuits",

issn = "0018-9200",

publisher = "IEEE",

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TY - JOUR

T1 - A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS

AU - van de Beek, R.C.H.

AU - Vaucher, Cicero S.

AU - Leenaerts, Domine M.W.

AU - Klumperink, Eric A.M.

AU - Nauta, Bram

PY - 2004/11

Y1 - 2004/11

N2 - This paper demonstrates a low-jitter clock multiplier unit that generates a 10-GHz output clock from a 2.5-GHz reference clock. An integrated 10-GHz LC oscillator is locked to the input clock, using a simple and fast phase detector circuit that overcomes the speed limitation of a conventional tri-state phase frequency detector due to the lack of an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18-μm CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8-V supply.

AB - This paper demonstrates a low-jitter clock multiplier unit that generates a 10-GHz output clock from a 2.5-GHz reference clock. An integrated 10-GHz LC oscillator is locked to the input clock, using a simple and fast phase detector circuit that overcomes the speed limitation of a conventional tri-state phase frequency detector due to the lack of an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18-μm CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8-V supply.

KW - CMOS

KW - IR-48798

KW - METIS-220546

KW - phase locked loops (PLL)

KW - phase frequency detector (PFD)

KW - clock multiplier unit (CMU)

KW - clock multiplication

KW - voltage-controlled Oscillator (VCO)

KW - frequency detector

KW - EWI-14464

KW - Charge pump

KW - low jitter

KW - frequency synthesizer

KW - frequency multiplication

KW - Phase Noise

KW - Phase Detector

KW - High speed

KW - Low noise

KW - Clock Generation

U2 - 10.1109/JSSC.2004.835833

DO - 10.1109/JSSC.2004.835833

M3 - Article

VL - 39

SP - 1862

EP - 1872

JO - IEEE journal of solid-state circuits

JF - IEEE journal of solid-state circuits

SN - 0018-9200

IS - 11

ER -

A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS

Abstract

Keywords

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