A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18μm CMOS technology

R.C.H. van de Beek, Cicero S. Vaucher, Dominicus M.W. Leenaerts, Nenad Pavlovic, Ketan Mistry, Eric A.M. Klumperink, Bram Nauta

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    13 Citations (Scopus)
    83 Downloads (Pure)

    Abstract

    A fully integrated clock multiplier unit uses 100mW to generate a 10GHz output clock with 0.22ps RMS jitter, exceeding the SONET OC-192 jitter generation specifications. An LC VCO is controlled by a PLL employing a fast linear phase detector in combination with a frequency detector, both running at 2.5GHz. The jitter and power dissipation are lower than that of previous CMOS implementations.
    Original languageEnglish
    Title of host publicationIEEE International Solid-State Circuits Conference 2003 (ISSCC 2003)
    PublisherIEEE Computer Society
    Pages178-179
    Number of pages10
    ISBN (Print)0-7803-7707-9
    DOIs
    Publication statusPublished - Feb 2003
    EventIEEE International Solid-State Circuits Conference, ISSCC 2003 - San Francisco, United States
    Duration: 9 Feb 200313 Feb 2003

    Conference

    ConferenceIEEE International Solid-State Circuits Conference, ISSCC 2003
    Abbreviated titleISSCC
    CountryUnited States
    CitySan Francisco
    Period9/02/0313/02/03

    Keywords

    • IR-45864
    • EWI-14437
    • METIS-213441

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