A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18μm CMOS technology

R.C.H. van de Beek; Cicero S. Vaucher; Dominicus M.W. Leenaerts; Nenad Pavlovic; Ketan Mistry; Eric A.M. Klumperink; Bram Nauta

doi:10.1109/ISSCC.2003.1234256

A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18μm CMOS technology

R.C.H. van de Beek
, Cicero S. Vaucher
, Dominicus M.W. Leenaerts
, Nenad Pavlovic
, Ketan Mistry
, Eric A.M. Klumperink
, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

16 Citations (Scopus)

108 Downloads (Pure)

Abstract

A fully integrated clock multiplier unit uses 100mW to generate a 10GHz output clock with 0.22ps RMS jitter, exceeding the SONET OC-192 jitter generation specifications. An LC VCO is controlled by a PLL employing a fast linear phase detector in combination with a frequency detector, both running at 2.5GHz. The jitter and power dissipation are lower than that of previous CMOS implementations.

Original language	English
Title of host publication	IEEE International Solid-State Circuits Conference 2003 (ISSCC 2003)
Publisher	IEEE
Pages	178-179
Number of pages	10
ISBN (Print)	0-7803-7707-9
DOIs	https://doi.org/10.1109/ISSCC.2003.1234256
Publication status	Published - Feb 2003
Event	IEEE International Solid-State Circuits Conference, ISSCC 2003 - San Francisco, United States Duration: 9 Feb 2003 → 13 Feb 2003

Conference

Conference	IEEE International Solid-State Circuits Conference, ISSCC 2003
Abbreviated title	ISSCC
Country/Territory	United States
City	San Francisco
Period	9/02/03 → 13/02/03

Keywords

IR-45864
EWI-14437
METIS-213441

Access to Document

10.1109/ISSCC.2003.1234256

Cite this

@inproceedings{72534aba2bec43b5a5026300e1d5d895,

title = "A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18μm CMOS technology",

abstract = "A fully integrated clock multiplier unit uses 100mW to generate a 10GHz output clock with 0.22ps RMS jitter, exceeding the SONET OC-192 jitter generation specifications. An LC VCO is controlled by a PLL employing a fast linear phase detector in combination with a frequency detector, both running at 2.5GHz. The jitter and power dissipation are lower than that of previous CMOS implementations.",

keywords = "IR-45864, EWI-14437, METIS-213441",

author = "\{van de Beek\}, R.C.H. and Vaucher, \{Cicero S.\} and Leenaerts, \{Dominicus M.W.\} and Nenad Pavlovic and Ketan Mistry and Klumperink, \{Eric A.M.\} and Bram Nauta",

year = "2003",

month = feb,

doi = "10.1109/ISSCC.2003.1234256",

language = "English",

isbn = "0-7803-7707-9",

pages = "178--179",

booktitle = "IEEE International Solid-State Circuits Conference 2003 (ISSCC 2003)",

publisher = "IEEE",

address = "United States",

note = "IEEE International Solid-State Circuits Conference, ISSCC 2003, ISSCC ; Conference date: 09-02-2003 Through 13-02-2003",

}

van de Beek, RCH, Vaucher, CS, Leenaerts, DMW, Pavlovic, N, Mistry, K, Klumperink, EAM & Nauta, B 2003, A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18μm CMOS technology. in IEEE International Solid-State Circuits Conference 2003 (ISSCC 2003). IEEE, pp. 178-179, IEEE International Solid-State Circuits Conference, ISSCC 2003, San Francisco, California, United States, 9/02/03. https://doi.org/10.1109/ISSCC.2003.1234256

A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18μm CMOS technology. / van de Beek, R.C.H.; Vaucher, Cicero S.; Leenaerts, Dominicus M.W. et al.
IEEE International Solid-State Circuits Conference 2003 (ISSCC 2003). IEEE, 2003. p. 178-179.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18μm CMOS technology

AU - van de Beek, R.C.H.

AU - Vaucher, Cicero S.

AU - Leenaerts, Dominicus M.W.

AU - Pavlovic, Nenad

AU - Mistry, Ketan

AU - Klumperink, Eric A.M.

AU - Nauta, Bram

PY - 2003/2

Y1 - 2003/2

N2 - A fully integrated clock multiplier unit uses 100mW to generate a 10GHz output clock with 0.22ps RMS jitter, exceeding the SONET OC-192 jitter generation specifications. An LC VCO is controlled by a PLL employing a fast linear phase detector in combination with a frequency detector, both running at 2.5GHz. The jitter and power dissipation are lower than that of previous CMOS implementations.

AB - A fully integrated clock multiplier unit uses 100mW to generate a 10GHz output clock with 0.22ps RMS jitter, exceeding the SONET OC-192 jitter generation specifications. An LC VCO is controlled by a PLL employing a fast linear phase detector in combination with a frequency detector, both running at 2.5GHz. The jitter and power dissipation are lower than that of previous CMOS implementations.

KW - IR-45864

KW - EWI-14437

KW - METIS-213441

U2 - 10.1109/ISSCC.2003.1234256

DO - 10.1109/ISSCC.2003.1234256

M3 - Conference contribution

SN - 0-7803-7707-9

SP - 178

EP - 179

BT - IEEE International Solid-State Circuits Conference 2003 (ISSCC 2003)

PB - IEEE

T2 - IEEE International Solid-State Circuits Conference, ISSCC 2003

Y2 - 9 February 2003 through 13 February 2003

ER -

A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18μm CMOS technology

Abstract

Conference

Keywords

Access to Document

Fingerprint

Cite this