Abstract
A dynamic bias pre-amplifier based latch type comparator is designed in a 65nm CMOS process. Its performance is compared with the double-tail latch-type comparator fabricated on the same chip in terms of energy consumption, input referred noise and speed. Measurements demonstrate that the proposed dynamic bias pre-amplifier based comparator consumes 2.8 times less energy per comparator operation with a modest reduction in input referred noise and 40% increase in CLK-Q delay for small differential input voltages.
Original language | English |
---|---|
Title of host publication | ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference |
Place of Publication | Leuven, Belgium |
Publisher | IEEE Solid-State Circuits Society |
Pages | 71-74 |
Number of pages | 4 |
ISBN (Electronic) | 978-1-5090-5025-3 |
ISBN (Print) | 978-1-5090-5026-0 |
DOIs | |
Publication status | Published - 12 Sep 2017 |
Event | 43rd European Solid State Circuits Conference, ESSCIRC 2017 - KU Leuven Campus of Social Sciences, Leuven, Belgium Duration: 11 Sep 2017 → 14 Sep 2017 Conference number: 43 https://www.esscirc-essderc2017.org/ |
Conference
Conference | 43rd European Solid State Circuits Conference, ESSCIRC 2017 |
---|---|
Abbreviated title | ESSCIRC 2017 |
Country/Territory | Belgium |
City | Leuven |
Period | 11/09/17 → 14/09/17 |
Internet address |