A 30fJ/comparison dynamic bias comparator

Harijot Singh Bindra; Christiaan Egidius Lokin; Anne J. Annema; Bram  Nauta

doi:10.1109/ESSCIRC.2017.8094528

A 30fJ/comparison dynamic bias comparator

Harijot Singh Bindra, Christiaan Egidius Lokin, Anne J. Annema, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

19 Citations (Scopus)

1222 Downloads (Pure)

Abstract

A dynamic bias pre-amplifier based latch type comparator is designed in a 65nm CMOS process. Its performance is compared with the double-tail latch-type comparator fabricated on the same chip in terms of energy consumption, input referred noise and speed. Measurements demonstrate that the proposed dynamic bias pre-amplifier based comparator consumes 2.8 times less energy per comparator operation with a modest reduction in input referred noise and 40% increase in CLK-Q delay for small differential input voltages.

Original language	English
Title of host publication	ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference
Place of Publication	Leuven, Belgium
Publisher	IEEE Solid-State Circuits Society
Pages	71-74
Number of pages	4
ISBN (Electronic)	978-1-5090-5025-3
ISBN (Print)	978-1-5090-5026-0
DOIs	https://doi.org/10.1109/ESSCIRC.2017.8094528
Publication status	Published - 12 Sep 2017
Event	43rd European Solid State Circuits Conference, ESSCIRC 2017 - KU Leuven Campus of Social Sciences, Leuven, Belgium Duration: 11 Sep 2017 → 14 Sep 2017 Conference number: 43 https://www.esscirc-essderc2017.org/

Conference

Conference	43rd European Solid State Circuits Conference, ESSCIRC 2017
Abbreviated title	ESSCIRC 2017
Country/Territory	Belgium
City	Leuven
Period	11/09/17 → 14/09/17
Internet address	https://www.esscirc-essderc2017.org/

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10.1109/ESSCIRC.2017.8094528

ESSCIRC 2017 H.S. Bindra A 30 fj comparison dynamic bias comparatorAccepted author version, 1.1 MB

Cite this

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title = "A 30fJ/comparison dynamic bias comparator",

abstract = "A dynamic bias pre-amplifier based latch type comparator is designed in a 65nm CMOS process. Its performance is compared with the double-tail latch-type comparator fabricated on the same chip in terms of energy consumption, input referred noise and speed. Measurements demonstrate that the proposed dynamic bias pre-amplifier based comparator consumes 2.8 times less energy per comparator operation with a modest reduction in input referred noise and 40% increase in CLK-Q delay for small differential input voltages. ",

author = "Bindra, {Harijot Singh} and Lokin, {Christiaan Egidius} and Annema, {Anne J.} and Bram Nauta",

year = "2017",

month = sep,

day = "12",

doi = "10.1109/ESSCIRC.2017.8094528",

language = "English",

isbn = "978-1-5090-5026-0 ",

pages = "71--74",

booktitle = "ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference",

publisher = "IEEE Solid-State Circuits Society",

note = "43rd European Solid State Circuits Conference, ESSCIRC 2017, ESSCIRC 2017 ; Conference date: 11-09-2017 Through 14-09-2017",

url = "https://www.esscirc-essderc2017.org/",

}

A 30fJ/comparison dynamic bias comparator. / Bindra, Harijot Singh; Lokin, Christiaan Egidius; Annema, Anne J.; Nauta, Bram .

ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference . Leuven, Belgium : IEEE Solid-State Circuits Society, 2017. p. 71-74.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A 30fJ/comparison dynamic bias comparator

AU - Bindra, Harijot Singh

AU - Lokin, Christiaan Egidius

AU - Annema, Anne J.

AU - Nauta, Bram

N1 - Conference code: 43

PY - 2017/9/12

Y1 - 2017/9/12

N2 - A dynamic bias pre-amplifier based latch type comparator is designed in a 65nm CMOS process. Its performance is compared with the double-tail latch-type comparator fabricated on the same chip in terms of energy consumption, input referred noise and speed. Measurements demonstrate that the proposed dynamic bias pre-amplifier based comparator consumes 2.8 times less energy per comparator operation with a modest reduction in input referred noise and 40% increase in CLK-Q delay for small differential input voltages.

AB - A dynamic bias pre-amplifier based latch type comparator is designed in a 65nm CMOS process. Its performance is compared with the double-tail latch-type comparator fabricated on the same chip in terms of energy consumption, input referred noise and speed. Measurements demonstrate that the proposed dynamic bias pre-amplifier based comparator consumes 2.8 times less energy per comparator operation with a modest reduction in input referred noise and 40% increase in CLK-Q delay for small differential input voltages.

U2 - 10.1109/ESSCIRC.2017.8094528

DO - 10.1109/ESSCIRC.2017.8094528

M3 - Conference contribution

SN - 978-1-5090-5026-0

SP - 71

EP - 74

BT - ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference

PB - IEEE Solid-State Circuits Society

CY - Leuven, Belgium

T2 - 43rd European Solid State Circuits Conference, ESSCIRC 2017

Y2 - 11 September 2017 through 14 September 2017

ER -

A 30fJ/comparison dynamic bias comparator

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