A 30fJ/comparison dynamic bias comparator

Harijot Singh Bindra, Christiaan Egidius Lokin, Anne J. Annema, Bram Nauta

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    19 Citations (Scopus)
    1222 Downloads (Pure)


    A dynamic bias pre-amplifier based latch type comparator is designed in a 65nm CMOS process. Its performance is compared with the double-tail latch-type comparator fabricated on the same chip in terms of energy consumption, input referred noise and speed. Measurements demonstrate that the proposed dynamic bias pre-amplifier based comparator consumes 2.8 times less energy per comparator operation with a modest reduction in input referred noise and 40% increase in CLK-Q delay for small differential input voltages.
    Original languageEnglish
    Title of host publicationESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference
    Place of PublicationLeuven, Belgium
    PublisherIEEE Solid-State Circuits Society
    Number of pages4
    ISBN (Electronic)978-1-5090-5025-3
    ISBN (Print)978-1-5090-5026-0
    Publication statusPublished - 12 Sep 2017
    Event43rd European Solid State Circuits Conference, ESSCIRC 2017 - KU Leuven Campus of Social Sciences, Leuven, Belgium
    Duration: 11 Sep 201714 Sep 2017
    Conference number: 43


    Conference43rd European Solid State Circuits Conference, ESSCIRC 2017
    Abbreviated titleESSCIRC 2017
    Internet address


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